1*7fbeb642SPhil Edworthy #ifndef _ASM_CPU_SH7264_H_ 2*7fbeb642SPhil Edworthy #define _ASM_CPU_SH7264_H_ 3*7fbeb642SPhil Edworthy 4*7fbeb642SPhil Edworthy /* Cache */ 5*7fbeb642SPhil Edworthy #define CCR1 0xFFFC1000 6*7fbeb642SPhil Edworthy #define CCR CCR1 7*7fbeb642SPhil Edworthy 8*7fbeb642SPhil Edworthy /* PFC */ 9*7fbeb642SPhil Edworthy #define PACR 0xA4050100 10*7fbeb642SPhil Edworthy #define PBCR 0xA4050102 11*7fbeb642SPhil Edworthy #define PCCR 0xA4050104 12*7fbeb642SPhil Edworthy #define PETCR 0xA4050106 13*7fbeb642SPhil Edworthy 14*7fbeb642SPhil Edworthy /* Port Data Registers */ 15*7fbeb642SPhil Edworthy #define PADR 0xA4050120 16*7fbeb642SPhil Edworthy #define PBDR 0xA4050122 17*7fbeb642SPhil Edworthy #define PCDR 0xA4050124 18*7fbeb642SPhil Edworthy 19*7fbeb642SPhil Edworthy /* BSC */ 20*7fbeb642SPhil Edworthy 21*7fbeb642SPhil Edworthy /* SDRAM controller */ 22*7fbeb642SPhil Edworthy 23*7fbeb642SPhil Edworthy /* SCIF */ 24*7fbeb642SPhil Edworthy #define SCSMR_3 0xFFFE9800 25*7fbeb642SPhil Edworthy #define SCIF3_BASE SCSMR_3 26*7fbeb642SPhil Edworthy 27*7fbeb642SPhil Edworthy /* Timer(CMT) */ 28*7fbeb642SPhil Edworthy #define CMSTR 0xFFFEC000 29*7fbeb642SPhil Edworthy #define CMCSR_0 0xFFFEC002 30*7fbeb642SPhil Edworthy #define CMCNT_0 0xFFFEC004 31*7fbeb642SPhil Edworthy #define CMCOR_0 0xFFFEC006 32*7fbeb642SPhil Edworthy #define CMCSR_1 0xFFFEC008 33*7fbeb642SPhil Edworthy #define CMCNT_1 0xFFFEC00A 34*7fbeb642SPhil Edworthy #define CMCOR_1 0xFFFEC00C 35*7fbeb642SPhil Edworthy 36*7fbeb642SPhil Edworthy /* On chip oscillator circuits */ 37*7fbeb642SPhil Edworthy #define FRQCR 0xA415FF80 38*7fbeb642SPhil Edworthy #define WTCNT 0xA415FF84 39*7fbeb642SPhil Edworthy #define WTCSR 0xA415FF86 40*7fbeb642SPhil Edworthy 41*7fbeb642SPhil Edworthy #endif /* _ASM_CPU_SH7264_H_ */ 42