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Searched refs:CACHE_LINE_SIZE (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/arch/arm/mm/
H A Dcache-feroceon-l2.c134 #define CACHE_LINE_SIZE 32 macro
143 BUG_ON(start & (CACHE_LINE_SIZE - 1)); in calc_range_end()
144 BUG_ON(end & (CACHE_LINE_SIZE - 1)); in calc_range_end()
173 if (start & (CACHE_LINE_SIZE - 1)) { in feroceon_l2_inv_range()
174 l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); in feroceon_l2_inv_range()
175 start = (start | (CACHE_LINE_SIZE - 1)) + 1; in feroceon_l2_inv_range()
181 if (start < end && end & (CACHE_LINE_SIZE - 1)) { in feroceon_l2_inv_range()
182 l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); in feroceon_l2_inv_range()
183 end &= ~(CACHE_LINE_SIZE - 1); in feroceon_l2_inv_range()
191 l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); in feroceon_l2_inv_range()
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H A Dcache-tauros2.c64 #define CACHE_LINE_SIZE 32 macro
71 if (start & (CACHE_LINE_SIZE - 1)) { in tauros2_inv_range()
72 tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); in tauros2_inv_range()
73 start = (start | (CACHE_LINE_SIZE - 1)) + 1; in tauros2_inv_range()
79 if (end & (CACHE_LINE_SIZE - 1)) { in tauros2_inv_range()
80 tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); in tauros2_inv_range()
81 end &= ~(CACHE_LINE_SIZE - 1); in tauros2_inv_range()
89 start += CACHE_LINE_SIZE; in tauros2_inv_range()
97 start &= ~(CACHE_LINE_SIZE - 1); in tauros2_clean_range()
100 start += CACHE_LINE_SIZE; in tauros2_clean_range()
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H A Dcache-xsc3l2.c15 #define CACHE_LINE_SIZE 32 macro
100 if (start & (CACHE_LINE_SIZE - 1)) { in xsc3_l2_inv_range()
101 vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr); in xsc3_l2_inv_range()
104 start = (start | (CACHE_LINE_SIZE - 1)) + 1; in xsc3_l2_inv_range()
110 while (start < (end & ~(CACHE_LINE_SIZE - 1))) { in xsc3_l2_inv_range()
113 start += CACHE_LINE_SIZE; in xsc3_l2_inv_range()
136 start &= ~(CACHE_LINE_SIZE - 1); in xsc3_l2_clean_range()
140 start += CACHE_LINE_SIZE; in xsc3_l2_clean_range()
179 start &= ~(CACHE_LINE_SIZE - 1); in xsc3_l2_flush_range()
184 start += CACHE_LINE_SIZE; in xsc3_l2_flush_range()
H A Dcache-l2x0.c37 #define CACHE_LINE_SIZE 32 macro
183 start += CACHE_LINE_SIZE; in __l2c210_op_pa_range()
191 if (start & (CACHE_LINE_SIZE - 1)) { in l2c210_inv_range()
192 start &= ~(CACHE_LINE_SIZE - 1); in l2c210_inv_range()
194 start += CACHE_LINE_SIZE; in l2c210_inv_range()
197 if (end & (CACHE_LINE_SIZE - 1)) { in l2c210_inv_range()
198 end &= ~(CACHE_LINE_SIZE - 1); in l2c210_inv_range()
210 start &= ~(CACHE_LINE_SIZE - 1); in l2c210_clean_range()
219 start &= ~(CACHE_LINE_SIZE - 1); in l2c210_flush_range()
295 start += CACHE_LINE_SIZE; in l2c220_op_pa_range()
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H A Dcache-v6.S18 #define CACHE_LINE_SIZE 32 macro
134 bic r0, r0, #CACHE_LINE_SIZE - 1
137 add r0, r0, #CACHE_LINE_SIZE
/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dcache.S10 #ifndef CACHE_LINE_SIZE
11 # define CACHE_LINE_SIZE L1_CACHE_BYTES macro
14 #if CACHE_LINE_SIZE == 128
16 #elif CACHE_LINE_SIZE == 32
18 #elif CACHE_LINE_SIZE == 16
20 #elif CACHE_LINE_SIZE == 8
57 lis r5,CACHE_LINE_SIZE
62 lis r5,CACHE_LINE_SIZE
75 li r5,CACHE_LINE_SIZE-1
84 addi r3,r3,CACHE_LINE_SIZE
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/openbmc/u-boot/arch/nds32/lib/
H A Dcache.c30 static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) in CACHE_LINE_SIZE() function
45 line_size = CACHE_LINE_SIZE(ICACHE); in invalidate_icache_all()
65 line_size = CACHE_LINE_SIZE(ICACHE); in invalidate_icache_range()
140 line_size = CACHE_LINE_SIZE(DCACHE); in dcache_wbinval_all()
163 line_size = CACHE_LINE_SIZE(DCACHE); in flush_dcache_range()
178 line_size = CACHE_LINE_SIZE(DCACHE); in invalidate_dcache_range()
/openbmc/linux/arch/m68k/coldfire/
H A Dcache.c41 : "i" (CACHE_LINE_SIZE), in mcf_cache_push()
/openbmc/linux/arch/m68k/include/asm/
H A Dm53xxacr.h65 #define CACHE_LINE_SIZE 16 /* 16 byte line size */ macro
H A Dm54xxacr.h65 #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ macro
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_sdram.c574 flush_l1_v7(line + CACHE_LINE_SIZE); in ddr3_flush_l1_line()
578 flush_l1_v6(line + CACHE_LINE_SIZE); in ddr3_flush_l1_line()
H A Dddr3_hw_training.h89 #define CACHE_LINE_SIZE 0x20 macro
/openbmc/linux/Documentation/scsi/
H A DChangeLog.ncr53c8xx351 Use a single alignment boundary (CACHE_LINE_SIZE) for data