1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2ff9112dfSStefan Roese /* 3ff9112dfSStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4ff9112dfSStefan Roese */ 5ff9112dfSStefan Roese 6ff9112dfSStefan Roese #ifndef __DDR3_TRAINING_H 7ff9112dfSStefan Roese #define __DDR3_TRAINING_H 8ff9112dfSStefan Roese 9ff9112dfSStefan Roese #include "ddr3_init.h" 10ff9112dfSStefan Roese 11ff9112dfSStefan Roese #ifdef MV88F78X60 12ff9112dfSStefan Roese #include "ddr3_axp.h" 13ff9112dfSStefan Roese #elif defined(MV88F67XX) 14ff9112dfSStefan Roese #include "ddr3_a370.h" 15ff9112dfSStefan Roese #elif defined(MV88F672X) 16ff9112dfSStefan Roese #include "ddr3_a375.h" 17ff9112dfSStefan Roese #endif 18ff9112dfSStefan Roese 19ff9112dfSStefan Roese /* The following is a list of Marvell status */ 20ff9112dfSStefan Roese #define MV_ERROR (-1) 21ff9112dfSStefan Roese #define MV_OK (0x00) /* Operation succeeded */ 22ff9112dfSStefan Roese #define MV_FAIL (0x01) /* Operation failed */ 23ff9112dfSStefan Roese #define MV_BAD_VALUE (0x02) /* Illegal value (general) */ 24ff9112dfSStefan Roese #define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ 25ff9112dfSStefan Roese #define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ 26ff9112dfSStefan Roese #define MV_BAD_PTR (0x05) /* Illegal pointer value */ 27ff9112dfSStefan Roese #define MV_BAD_SIZE (0x06) /* Illegal size */ 28ff9112dfSStefan Roese #define MV_BAD_STATE (0x07) /* Illegal state of state machine */ 29ff9112dfSStefan Roese #define MV_SET_ERROR (0x08) /* Set operation failed */ 30ff9112dfSStefan Roese #define MV_GET_ERROR (0x09) /* Get operation failed */ 31ff9112dfSStefan Roese #define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ 32ff9112dfSStefan Roese #define MV_NOT_FOUND (0x0B) /* Item not found */ 33ff9112dfSStefan Roese #define MV_NO_MORE (0x0C) /* No more items found */ 34ff9112dfSStefan Roese #define MV_NO_SUCH (0x0D) /* No such item */ 35ff9112dfSStefan Roese #define MV_TIMEOUT (0x0E) /* Time Out */ 36ff9112dfSStefan Roese #define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ 37ff9112dfSStefan Roese #define MV_NOT_SUPPORTED (0x10) /* This request is not support */ 38ff9112dfSStefan Roese #define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/ 39ff9112dfSStefan Roese #define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ 40ff9112dfSStefan Roese #define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ 41ff9112dfSStefan Roese #define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ 42ff9112dfSStefan Roese #define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ 43eae4b2b6SVagrant Cascadian #define MV_INIT_ERROR (0x16) /* Error occurred while INIT process */ 44ff9112dfSStefan Roese #define MV_HW_ERROR (0x17) /* Hardware error */ 45ff9112dfSStefan Roese #define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ 46ff9112dfSStefan Roese #define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ 47ff9112dfSStefan Roese #define MV_NOT_READY (0x1A) /* The other side is not ready yet */ 48ff9112dfSStefan Roese #define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ 49ff9112dfSStefan Roese #define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ 50ff9112dfSStefan Roese #define MV_NOT_STARTED (0x1D) /* Not started yet */ 51ff9112dfSStefan Roese #define MV_BUSY (0x1E) /* Item is busy. */ 52ff9112dfSStefan Roese #define MV_TERMINATE (0x1F) /* Item terminates it's work. */ 53ff9112dfSStefan Roese #define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ 54ff9112dfSStefan Roese #define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ 55ff9112dfSStefan Roese #define MV_WRITE_PROTECT (0x22) /* Write protected */ 56ff9112dfSStefan Roese 57ff9112dfSStefan Roese #define MV_INVALID (int)(-1) 58ff9112dfSStefan Roese 59ff9112dfSStefan Roese /* 60ff9112dfSStefan Roese * Debug (Enable/Disable modules) and Error report 61ff9112dfSStefan Roese */ 62ff9112dfSStefan Roese 63ff9112dfSStefan Roese #ifdef BASIC_DEBUG 64ff9112dfSStefan Roese #define MV_DEBUG_WL 65ff9112dfSStefan Roese #define MV_DEBUG_RL 66ff9112dfSStefan Roese #define MV_DEBUG_DQS_RESULTS 67ff9112dfSStefan Roese #endif 68ff9112dfSStefan Roese 69ff9112dfSStefan Roese #ifdef FULL_DEBUG 70ff9112dfSStefan Roese #define MV_DEBUG_WL 71ff9112dfSStefan Roese #define MV_DEBUG_RL 72ff9112dfSStefan Roese #define MV_DEBUG_DQS 73ff9112dfSStefan Roese 74ff9112dfSStefan Roese #define MV_DEBUG_PBS 75ff9112dfSStefan Roese #define MV_DEBUG_DFS 76ff9112dfSStefan Roese #define MV_DEBUG_MAIN_FULL 77ff9112dfSStefan Roese #define MV_DEBUG_DFS_FULL 78ff9112dfSStefan Roese #define MV_DEBUG_DQS_FULL 79ff9112dfSStefan Roese #define MV_DEBUG_RL_FULL 80ff9112dfSStefan Roese #define MV_DEBUG_WL_FULL 81ff9112dfSStefan Roese #endif 82ff9112dfSStefan Roese 83ff9112dfSStefan Roese /* 84ff9112dfSStefan Roese * General Consts 85ff9112dfSStefan Roese */ 86ff9112dfSStefan Roese 87ff9112dfSStefan Roese #define SDRAM_READ_WRITE_LEN_IN_WORDS 16 88ff9112dfSStefan Roese #define SDRAM_READ_WRITE_LEN_IN_DOUBLE_WORDS 8 89ff9112dfSStefan Roese #define CACHE_LINE_SIZE 0x20 90ff9112dfSStefan Roese 91ff9112dfSStefan Roese #define SDRAM_CS_BASE 0x0 92ff9112dfSStefan Roese 93ff9112dfSStefan Roese #define SRAM_BASE 0x40000000 94ff9112dfSStefan Roese #define SRAM_SIZE 0xFFF 95ff9112dfSStefan Roese 96ff9112dfSStefan Roese #define LEN_64BIT_STD_PATTERN 16 97ff9112dfSStefan Roese #define LEN_64BIT_KILLER_PATTERN 128 98ff9112dfSStefan Roese #define LEN_64BIT_SPECIAL_PATTERN 128 99ff9112dfSStefan Roese #define LEN_64BIT_PBS_PATTERN 16 100ff9112dfSStefan Roese #define LEN_WL_SUP_PATTERN 32 101ff9112dfSStefan Roese 102ff9112dfSStefan Roese #define LEN_16BIT_STD_PATTERN 4 103ff9112dfSStefan Roese #define LEN_16BIT_KILLER_PATTERN 128 104ff9112dfSStefan Roese #define LEN_16BIT_SPECIAL_PATTERN 128 105ff9112dfSStefan Roese #define LEN_16BIT_PBS_PATTERN 4 106ff9112dfSStefan Roese 107ff9112dfSStefan Roese #define CMP_BYTE_SHIFT 8 108ff9112dfSStefan Roese #define CMP_BYTE_MASK 0xFF 109ff9112dfSStefan Roese #define PUP_SIZE 8 110ff9112dfSStefan Roese 111ff9112dfSStefan Roese #define S 0 112ff9112dfSStefan Roese #define C 1 113ff9112dfSStefan Roese #define P 2 114ff9112dfSStefan Roese #define D 3 115ff9112dfSStefan Roese #define DQS 6 116ff9112dfSStefan Roese #define PS 2 117ff9112dfSStefan Roese #define DS 3 118ff9112dfSStefan Roese #define PE 4 119ff9112dfSStefan Roese #define DE 5 120ff9112dfSStefan Roese 121ff9112dfSStefan Roese #define CS0 0 122ff9112dfSStefan Roese #define MAX_DIMM_NUM 2 123ff9112dfSStefan Roese #define MAX_DELAY 0x1F 124ff9112dfSStefan Roese 125ff9112dfSStefan Roese /* 126ff9112dfSStefan Roese * Invertion limit and phase1 limit are WA for the RL @ 1:1 design bug - 127ff9112dfSStefan Roese * Armada 370 & AXP Z1 128ff9112dfSStefan Roese */ 129ff9112dfSStefan Roese #define MAX_DELAY_INV_LIMIT 0x5 130ff9112dfSStefan Roese #define MIN_DELAY_PHASE_1_LIMIT 0x10 131ff9112dfSStefan Roese 132ff9112dfSStefan Roese #define MAX_DELAY_INV (0x3F - MAX_DELAY_INV_LIMIT) 133ff9112dfSStefan Roese #define MIN_DELAY 0 134ff9112dfSStefan Roese #define MAX_PUP_NUM 9 135ff9112dfSStefan Roese #define ECC_PUP 8 136ff9112dfSStefan Roese #define DQ_NUM 8 137ff9112dfSStefan Roese #define DQS_DQ_NUM 8 138ff9112dfSStefan Roese #define INIT_WL_DELAY 13 139ff9112dfSStefan Roese #define INIT_RL_DELAY 15 140ff9112dfSStefan Roese #define TWLMRD_DELAY 20 141ff9112dfSStefan Roese #define TCLK_3_DELAY 3 142ff9112dfSStefan Roese #define ECC_BIT 8 143ff9112dfSStefan Roese #define DMA_SIZE 64 144ff9112dfSStefan Roese #define MV_DMA_0 0 145ff9112dfSStefan Roese #define MAX_TRAINING_RETRY 10 146ff9112dfSStefan Roese 147ff9112dfSStefan Roese #define PUP_RL_MODE 0x2 148ff9112dfSStefan Roese #define PUP_WL_MODE 0 149ff9112dfSStefan Roese #define PUP_PBS_TX 0x10 150ff9112dfSStefan Roese #define PUP_PBS_TX_DM 0x1A 151ff9112dfSStefan Roese #define PUP_PBS_RX 0x30 152ff9112dfSStefan Roese #define PUP_DQS_WR 0x1 153ff9112dfSStefan Roese #define PUP_DQS_RD 0x3 154ff9112dfSStefan Roese #define PUP_BC 10 155ff9112dfSStefan Roese #define PUP_DELAY_MASK 0x1F 156ff9112dfSStefan Roese #define PUP_PHASE_MASK 0x7 157ff9112dfSStefan Roese #define PUP_NUM_64BIT 8 158ff9112dfSStefan Roese #define PUP_NUM_32BIT 4 159ff9112dfSStefan Roese #define PUP_NUM_16BIT 2 160ff9112dfSStefan Roese 161ff9112dfSStefan Roese /* control PHY registers */ 162ff9112dfSStefan Roese #define CNTRL_PUP_DESKEW 0x10 163ff9112dfSStefan Roese 164ff9112dfSStefan Roese /* WL */ 165ff9112dfSStefan Roese #define COUNT_WL_HI_FREQ 2 166ff9112dfSStefan Roese #define COUNT_WL 2 167ff9112dfSStefan Roese #define COUNT_WL_RFRS 9 168ff9112dfSStefan Roese #define WL_HI_FREQ_SHIFT 2 169ff9112dfSStefan Roese #define WL_HI_FREQ_STATE 1 170ff9112dfSStefan Roese #define COUNT_HW_WL 2 171ff9112dfSStefan Roese 172ff9112dfSStefan Roese /* RL */ 173ff9112dfSStefan Roese /* 174ff9112dfSStefan Roese * RL_MODE - this define uses the RL mode SW RL instead of the functional 175ff9112dfSStefan Roese * window SW RL 176ff9112dfSStefan Roese */ 177ff9112dfSStefan Roese #define RL_MODE 178ff9112dfSStefan Roese #define RL_WINDOW_WA 179ff9112dfSStefan Roese #define MAX_PHASE_1TO1 2 180ff9112dfSStefan Roese #define MAX_PHASE_2TO1 4 181ff9112dfSStefan Roese 182ff9112dfSStefan Roese #define MAX_PHASE_RL_UL_1TO1 0 183ff9112dfSStefan Roese #define MAX_PHASE_RL_L_1TO1 4 184ff9112dfSStefan Roese #define MAX_PHASE_RL_UL_2TO1 3 185ff9112dfSStefan Roese #define MAX_PHASE_RL_L_2TO1 7 186ff9112dfSStefan Roese 187ff9112dfSStefan Roese #define RL_UNLOCK_STATE 0 188ff9112dfSStefan Roese #define RL_WINDOW_STATE 1 189ff9112dfSStefan Roese #define RL_FINAL_STATE 2 190ff9112dfSStefan Roese #define RL_RETRY_COUNT 2 191ff9112dfSStefan Roese #define COUNT_HW_RL 2 192ff9112dfSStefan Roese 193ff9112dfSStefan Roese /* PBS */ 194ff9112dfSStefan Roese #define MAX_PBS 31 195ff9112dfSStefan Roese #define MIN_PBS 0 196ff9112dfSStefan Roese #define COUNT_PBS_PATTERN 2 197ff9112dfSStefan Roese #define COUNT_PBS_STARTOVER 2 198ff9112dfSStefan Roese #define COUNT_PBS_REPEAT 3 199ff9112dfSStefan Roese #define COUNT_PBS_COMP_RETRY_NUM 2 200ff9112dfSStefan Roese #define PBS_DIFF_LIMIT 31 201ff9112dfSStefan Roese #define PATTERN_PBS_TX_A 0x55555555 202ff9112dfSStefan Roese #define PATTERN_PBS_TX_B 0xAAAAAAAA 203ff9112dfSStefan Roese 204ff9112dfSStefan Roese /* DQS */ 205ff9112dfSStefan Roese #define ADLL_ERROR 0x55 206ff9112dfSStefan Roese #define ADLL_MAX 31 207ff9112dfSStefan Roese #define ADLL_MIN 0 208ff9112dfSStefan Roese #define MIN_WIN_SIZE 4 209ff9112dfSStefan Roese #define VALID_WIN_THRS MIN_WIN_SIZE 210ff9112dfSStefan Roese 211ff9112dfSStefan Roese #define MODE_2TO1 1 212ff9112dfSStefan Roese #define MODE_1TO1 0 213ff9112dfSStefan Roese 214ff9112dfSStefan Roese /* 215ff9112dfSStefan Roese * Macros 216ff9112dfSStefan Roese */ 217ff9112dfSStefan Roese #define IS_PUP_ACTIVE(_data_, _pup_) (((_data_) >> (_pup_)) & 0x1) 218ff9112dfSStefan Roese 219ff9112dfSStefan Roese /* 220ff9112dfSStefan Roese * Internal ERROR codes 221ff9112dfSStefan Roese */ 222ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_WR_LVL_HW 0xDD302001 223ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_LOAD_PATTERNS 0xDD302002 224ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_WR_LVL_HI_FREQ 0xDD302003 225ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_DFS_H2L 0xDD302004 226ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_DRAM_COMPARE 0xDD302005 227ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_WIN_LIMITS 0xDD302006 228ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_PUP_RANGE 0xDD302025 229ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_DQS_LOW_LIMIT_SEARCH 0xDD302007 230ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_DQS_HIGH_LIMIT_SEARCH 0xDD302008 231ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_DQS_PATTERN 0xDD302009 232ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_PBS_ADLL_SHR_1PHASE 0xDD302010 233ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_PBS_TX_MAX_VAL 0xDD302011 234ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_PBS_RX_PER_BIT 0xDD302012 235ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_PBS_TX_PER_BIT 0xDD302013 236ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_PBS_RX_MAX_VAL 0xDD302014 237ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_SRAM_CMP 0xDD302015 238ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_MAX_VAL 0xDD302016 239ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PATTERN 0xDD302017 240ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PUP_UNLOCK 0xDD302018 241ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_RD_LVL_PUP_UNLOCK 0xDD302019 242ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_WR_LVL_SW 0xDD302020 243ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_PRBS_RX 0xDD302021 244ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_DQS_RX 0xDD302022 245ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_PRBS_TX 0xDD302023 246ff9112dfSStefan Roese #define MV_DDR3_TRAINING_ERR_DQS_TX 0xDD302024 247ff9112dfSStefan Roese 248ff9112dfSStefan Roese /* 249ff9112dfSStefan Roese * DRAM information structure 250ff9112dfSStefan Roese */ 251ff9112dfSStefan Roese typedef struct dram_info { 252ff9112dfSStefan Roese u32 num_cs; 253ff9112dfSStefan Roese u32 cs_ena; 254ff9112dfSStefan Roese u32 num_of_std_pups; /* Q value = ddrWidth/8 - Without ECC!! */ 255ff9112dfSStefan Roese u32 num_of_total_pups; /* numOfStdPups + eccEna */ 256ff9112dfSStefan Roese u32 target_frequency; /* DDR Frequency */ 257ff9112dfSStefan Roese u32 ddr_width; /* 32/64 Bit or 16/32 Bit */ 258ff9112dfSStefan Roese u32 ecc_ena; /* 0/1 */ 259ff9112dfSStefan Roese u32 wl_val[MAX_CS][MAX_PUP_NUM][7]; 260ff9112dfSStefan Roese u32 rl_val[MAX_CS][MAX_PUP_NUM][7]; 261ff9112dfSStefan Roese u32 rl_max_phase; 262ff9112dfSStefan Roese u32 rl_min_phase; 263ff9112dfSStefan Roese u32 wl_max_phase; 264ff9112dfSStefan Roese u32 wl_min_phase; 265ff9112dfSStefan Roese u32 rd_smpl_dly; 266ff9112dfSStefan Roese u32 rd_rdy_dly; 267ff9112dfSStefan Roese u32 cl; 268ff9112dfSStefan Roese u32 cwl; 269ff9112dfSStefan Roese u32 mode_2t; 270ff9112dfSStefan Roese int rl400_bug; 271ff9112dfSStefan Roese int multi_cs_mr_support; 272ff9112dfSStefan Roese int reg_dimm; 273ff9112dfSStefan Roese } MV_DRAM_INFO; 274ff9112dfSStefan Roese 275ff9112dfSStefan Roese enum training_modes { 276ff9112dfSStefan Roese DQS_WR_MODE, 277ff9112dfSStefan Roese WL_MODE_, 278ff9112dfSStefan Roese RL_MODE_, 279ff9112dfSStefan Roese DQS_RD_MODE, 280ff9112dfSStefan Roese PBS_TX_DM_MODE, 281ff9112dfSStefan Roese PBS_TX_MODE, 282ff9112dfSStefan Roese PBS_RX_MODE, 283ff9112dfSStefan Roese MAX_TRAINING_MODE, 284ff9112dfSStefan Roese }; 285ff9112dfSStefan Roese 286ff9112dfSStefan Roese typedef struct dram_training_init { 287ff9112dfSStefan Roese u32 reg_addr; 288ff9112dfSStefan Roese u32 reg_value; 289ff9112dfSStefan Roese } MV_DRAM_TRAINING_INIT; 290ff9112dfSStefan Roese 291ff9112dfSStefan Roese typedef struct dram_mv_init { 292ff9112dfSStefan Roese u32 reg_addr; 293ff9112dfSStefan Roese u32 reg_value; 294ff9112dfSStefan Roese } MV_DRAM_MC_INIT; 295ff9112dfSStefan Roese 296ff9112dfSStefan Roese /* Board/Soc revisions define */ 297ff9112dfSStefan Roese enum board_rev { 298ff9112dfSStefan Roese Z1, 299ff9112dfSStefan Roese Z1_PCAC, 300ff9112dfSStefan Roese Z1_RD_SLED, 301ff9112dfSStefan Roese A0, 302ff9112dfSStefan Roese A0_AMC 303ff9112dfSStefan Roese }; 304ff9112dfSStefan Roese 305ff9112dfSStefan Roese typedef struct dram_modes { 306ff9112dfSStefan Roese char *mode_name; 307ff9112dfSStefan Roese u8 cpu_freq; 308ff9112dfSStefan Roese u8 fab_freq; 309ff9112dfSStefan Roese u8 chip_id; 310ff9112dfSStefan Roese int chip_board_rev; 311ff9112dfSStefan Roese MV_DRAM_MC_INIT *regs; 312ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT *vals; 313ff9112dfSStefan Roese } MV_DRAM_MODES; 314ff9112dfSStefan Roese 315ff9112dfSStefan Roese /* 316ff9112dfSStefan Roese * Function Declarations 317ff9112dfSStefan Roese */ 318ff9112dfSStefan Roese 319ff9112dfSStefan Roese u32 cache_inv(u32 addr); 320ff9112dfSStefan Roese void flush_l1_v7(u32 line); 321ff9112dfSStefan Roese void flush_l1_v6(u32 line); 322ff9112dfSStefan Roese 323ff9112dfSStefan Roese u32 ddr3_cl_to_valid_cl(u32 cl); 324ff9112dfSStefan Roese u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl); 325ff9112dfSStefan Roese 326ff9112dfSStefan Roese void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay); 327ff9112dfSStefan Roese u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup); 328ff9112dfSStefan Roese 329ff9112dfSStefan Roese int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked, int is_tx, 330ff9112dfSStefan Roese u32 pbs_pattern_idx, u32 pbs_curr_val, 331ff9112dfSStefan Roese u32 pbs_lock_val, u32 *skew_array, 332ff9112dfSStefan Roese u8 *unlock_pup_dq_array, u32 ecc); 333ff9112dfSStefan Roese 334ff9112dfSStefan Roese int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, 335ff9112dfSStefan Roese u32 *new_locked_pup, u32 *pattern, 336ff9112dfSStefan Roese u32 pattern_len, u32 sdram_offset, int write, 337ff9112dfSStefan Roese int mask, u32 *mask_pattern, int b_special_compare); 338ff9112dfSStefan Roese 339ff9112dfSStefan Roese int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, 340ff9112dfSStefan Roese u32 *new_locked_pup, u32 *pattern, u32 pattern_len, 341ff9112dfSStefan Roese u32 sdram_offset, int write, int mask, 342ff9112dfSStefan Roese u32 *mask_pattern, int b_special_compare); 343ff9112dfSStefan Roese 344ff9112dfSStefan Roese int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, 345ff9112dfSStefan Roese u32 *new_locked_pup, u32 *pattern, 346ff9112dfSStefan Roese u32 pattern_len, u32 sdram_offset, int write, 347ff9112dfSStefan Roese int mask, u32 *mask_pattern); 348ff9112dfSStefan Roese 349ff9112dfSStefan Roese int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, 350ff9112dfSStefan Roese u32 *new_locked_pup, u32 *pattern, 351ff9112dfSStefan Roese u32 sdram_offset); 352ff9112dfSStefan Roese int ddr3_dram_sram_read(u32 src, u32 dst, u32 len); 353ff9112dfSStefan Roese int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume); 354ff9112dfSStefan Roese 355ff9112dfSStefan Roese int ddr3_read_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info); 356ff9112dfSStefan Roese int ddr3_read_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info); 357ff9112dfSStefan Roese 358ff9112dfSStefan Roese int ddr3_write_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info); 359ff9112dfSStefan Roese int ddr3_write_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info); 360ff9112dfSStefan Roese int ddr3_write_leveling_hw_reg_dimm(u32 freq, MV_DRAM_INFO *dram_info); 361ff9112dfSStefan Roese int ddr3_wl_supplement(MV_DRAM_INFO *dram_info); 362ff9112dfSStefan Roese 363ff9112dfSStefan Roese int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info); 364ff9112dfSStefan Roese int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info); 365ff9112dfSStefan Roese 366ff9112dfSStefan Roese int ddr3_pbs_tx(MV_DRAM_INFO *dram_info); 367ff9112dfSStefan Roese int ddr3_pbs_rx(MV_DRAM_INFO *dram_info); 368ff9112dfSStefan Roese int ddr3_load_pbs_patterns(MV_DRAM_INFO *dram_info); 369ff9112dfSStefan Roese 370ff9112dfSStefan Roese int ddr3_dqs_centralization_rx(MV_DRAM_INFO *dram_info); 371ff9112dfSStefan Roese int ddr3_dqs_centralization_tx(MV_DRAM_INFO *dram_info); 372ff9112dfSStefan Roese int ddr3_load_dqs_patterns(MV_DRAM_INFO *dram_info); 373ff9112dfSStefan Roese 374ff9112dfSStefan Roese void ddr3_static_training_init(void); 375ff9112dfSStefan Roese 376ff9112dfSStefan Roese u8 ddr3_get_eprom_fabric(void); 377ff9112dfSStefan Roese void ddr3_set_performance_params(MV_DRAM_INFO *dram_info); 378ff9112dfSStefan Roese int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len); 379ff9112dfSStefan Roese void ddr3_save_training(MV_DRAM_INFO *dram_info); 380ff9112dfSStefan Roese int ddr3_read_training_results(void); 381ff9112dfSStefan Roese int ddr3_training_suspend_resume(MV_DRAM_INFO *dram_info); 382ff9112dfSStefan Roese int ddr3_get_min_max_read_sample_delay(u32 cs_enable, u32 reg, u32 *min, 383ff9112dfSStefan Roese u32 *max, u32 *cs_max); 384ff9112dfSStefan Roese int ddr3_get_min_max_rl_phase(MV_DRAM_INFO *dram_info, u32 *min, u32 *max, 385ff9112dfSStefan Roese u32 cs); 386ff9112dfSStefan Roese int ddr3_odt_activate(int activate); 387ff9112dfSStefan Roese int ddr3_odt_read_dynamic_config(MV_DRAM_INFO *dram_info); 388ff9112dfSStefan Roese void ddr3_print_freq(u32 freq); 389ff9112dfSStefan Roese void ddr3_reset_phy_read_fifo(void); 390ff9112dfSStefan Roese 391ff9112dfSStefan Roese #endif /* __DDR3_TRAINING_H */ 392