Home
last modified time | relevance | path

Searched refs:BIT_ULL (Results 1 – 25 of 527) sorted by relevance

12345678910>>...22

/openbmc/linux/drivers/gpu/drm/panfrost/
H A Dpanfrost_issues.h142 BIT_ULL(HW_ISSUE_9435))
145 BIT_ULL(HW_ISSUE_6367) | \
146 BIT_ULL(HW_ISSUE_6787) | \
147 BIT_ULL(HW_ISSUE_8408) | \
148 BIT_ULL(HW_ISSUE_9510) | \
149 BIT_ULL(HW_ISSUE_10649) | \
150 BIT_ULL(HW_ISSUE_10676) | \
151 BIT_ULL(HW_ISSUE_10883) | \
152 BIT_ULL(HW_ISSUE_11020) | \
153 BIT_ULL(HW_ISSUE_11035) | \
[all …]
H A Dpanfrost_features.h29 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
30 BIT_ULL(HW_FEATURE_V4))
37 BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
38 BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
39 BIT_ULL(HW_FEATURE_XAFFINITY) | \
40 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT))
51 BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
52 BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
53 BIT_ULL(HW_FEATURE_XAFFINITY) | \
54 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dcpu.h360 #define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
361 #define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
362 #define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
363 #define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
364 #define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
365 #define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
366 #define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
367 #define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
368 #define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
369 #define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dcavium.h120 #define MIO_EMM_DMA_FIFO_CFG_CLR BIT_ULL(16)
124 #define MIO_EMM_DMA_FIFO_CMD_RW BIT_ULL(62)
125 #define MIO_EMM_DMA_FIFO_CMD_INTDIS BIT_ULL(60)
126 #define MIO_EMM_DMA_FIFO_CMD_SWAP32 BIT_ULL(59)
127 #define MIO_EMM_DMA_FIFO_CMD_SWAP16 BIT_ULL(58)
128 #define MIO_EMM_DMA_FIFO_CMD_SWAP8 BIT_ULL(57)
129 #define MIO_EMM_DMA_FIFO_CMD_ENDIAN BIT_ULL(56)
132 #define MIO_EMM_CMD_SKIP_BUSY BIT_ULL(62)
134 #define MIO_EMM_CMD_VAL BIT_ULL(59)
135 #define MIO_EMM_CMD_DBUF BIT_ULL(55)
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/thunder/
H A Dthunder_bgx.h36 #define CMR_PKT_TX_EN BIT_ULL(13)
37 #define CMR_PKT_RX_EN BIT_ULL(14)
38 #define CMR_EN BIT_ULL(15)
40 #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6)
57 #define RX_DMACX_CAM_EN BIT_ULL(48)
87 #define SPU_CTL_LOW_POWER BIT_ULL(11)
88 #define SPU_CTL_LOOPBACK BIT_ULL(14)
89 #define SPU_CTL_RESET BIT_ULL(15)
91 #define SPU_STATUS1_RCV_LNK BIT_ULL(2)
93 #define SPU_STATUS2_RCVFLT BIT_ULL(10)
[all …]
/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h35 #define RISCV_IOMMU_FQ_HDR_PV BIT_ULL(32)
49 #define RISCV_IOMMU_PREQ_HDR_PV BIT_ULL(32)
50 #define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33)
51 #define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34)
72 #define RISCV_IOMMU_CAP_SV32 BIT_ULL(8)
73 #define RISCV_IOMMU_CAP_SV39 BIT_ULL(9)
74 #define RISCV_IOMMU_CAP_SV48 BIT_ULL(10)
75 #define RISCV_IOMMU_CAP_SV57 BIT_ULL(11)
76 #define RISCV_IOMMU_CAP_SV32X4 BIT_ULL(16)
77 #define RISCV_IOMMU_CAP_SV39X4 BIT_ULL(17)
[all …]
/openbmc/linux/drivers/infiniband/hw/irdma/
H A Ddefs.h384 #define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
387 #define IRDMA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60)
388 #define IRDMA_CQPSQ_QHASH_VLANVALID BIT_ULL(59)
390 #define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
391 #define IRDMA_CQPSQ_STATS_ALLOC_INST BIT_ULL(62)
392 #define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX BIT_ULL(60)
393 #define IRDMA_CQPSQ_STATS_USE_INST BIT_ULL(61)
397 #define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)
400 #define IRDMA_CQPSQ_WS_ENABLENODE BIT_ULL(62)
401 #define IRDMA_CQPSQ_WS_NODETYPE BIT_ULL(61)
[all …]
H A Duda_d.h17 #define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56)
18 #define IRDMA_UDA_QPSQ_INLINEDATAFLAG BIT_ULL(57)
22 #define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45)
23 #define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46)
24 #define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61)
28 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
39 #define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM BIT_ULL(45)
44 #define IRDMA_UDAQPC_IPV4_M BIT_ULL(3)
45 #define IRDMA_UDAQPC_INSERTVLANTAG BIT_ULL(5)
46 #define IRDMA_UDAQPC_ISQP1 BIT_ULL(6)
[all …]
/openbmc/linux/drivers/iommu/intel/
H A Dcap_audit.h13 #define CAP_FL5LP_MASK BIT_ULL(60)
14 #define CAP_PI_MASK BIT_ULL(59)
15 #define CAP_FL1GP_MASK BIT_ULL(56)
16 #define CAP_RD_MASK BIT_ULL(55)
17 #define CAP_WD_MASK BIT_ULL(54)
20 #define CAP_PSI_MASK BIT_ULL(39)
23 #define CAP_ZLR_MASK BIT_ULL(22)
26 #define CAP_CM_MASK BIT_ULL(7)
27 #define CAP_PHMR_MASK BIT_ULL(6)
28 #define CAP_PLMR_MASK BIT_ULL(5)
[all …]
/openbmc/linux/arch/loongarch/include/asm/
H A Dcpu.h103 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
104 #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
105 #define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)
106 #define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)
107 #define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX)
108 #define LOONGARCH_CPU_LASX BIT_ULL(CPU_FEATURE_LASX)
109 #define LOONGARCH_CPU_CRC32 BIT_ULL(CPU_FEATURE_CRC32)
110 #define LOONGARCH_CPU_COMPLEX BIT_ULL(CPU_FEATURE_COMPLEX)
111 #define LOONGARCH_CPU_CRYPTO BIT_ULL(CPU_FEATURE_CRYPTO)
112 #define LOONGARCH_CPU_LVZ BIT_ULL(CPU_FEATURE_LVZ)
[all …]
/openbmc/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.h746 #define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
747 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
748 BIT_ULL(MTK_CLK_TRGPLL))
749 #define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
750 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
751 BIT_ULL(MTK_CLK_GP2) | \
752 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
753 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
754 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
755 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
[all …]
/openbmc/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_dev.h16 #define KOMEDA_EVENT_VSYNC BIT_ULL(0)
17 #define KOMEDA_EVENT_FLIP BIT_ULL(1)
18 #define KOMEDA_EVENT_URUN BIT_ULL(2)
19 #define KOMEDA_EVENT_IBSY BIT_ULL(3)
20 #define KOMEDA_EVENT_OVR BIT_ULL(4)
21 #define KOMEDA_EVENT_EOW BIT_ULL(5)
22 #define KOMEDA_EVENT_MODE BIT_ULL(6)
23 #define KOMEDA_EVENT_FULL BIT_ULL(7)
24 #define KOMEDA_EVENT_EMPTY BIT_ULL(8)
26 #define KOMEDA_ERR_TETO BIT_ULL(14)
[all …]
/openbmc/linux/arch/x86/include/asm/
H A Dmce.h13 #define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */
14 #define MCG_EXT_P BIT_ULL(9) /* Extended registers available */
15 #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
19 #define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */
20 #define MCG_ELOG_P BIT_ULL(26) /* Extended error log supported */
21 #define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */
24 #define MCG_STATUS_RIPV BIT_ULL(0) /* restart ip valid */
25 #define MCG_STATUS_EIPV BIT_ULL(1) /* ip points to correct instruction */
26 #define MCG_STATUS_MCIP BIT_ULL(2) /* machine check in progress */
27 #define MCG_STATUS_LMCES BIT_ULL(3) /* LMCE signaled */
[all …]
H A Dmsr-index.h73 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
248 #define LBR_INFO_MISPRED BIT_ULL(63)
249 #define LBR_INFO_IN_TX BIT_ULL(62)
250 #define LBR_INFO_ABORT BIT_ULL(61)
251 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
277 #define PERF_CAP_PEBS_TRAP BIT_ULL(6)
278 #define PERF_CAP_ARCH_REG BIT_ULL(7)
280 #define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
300 #define RTIT_CTL_NOTNT BIT_ULL(55)
358 #define MSR_IA32_PASID_VALID BIT_ULL(31)
[all …]
/openbmc/linux/drivers/vdpa/pds/
H A Ddebugfs.c54 u64 mask = BIT_ULL(i); in print_feature_bits_all()
57 case BIT_ULL(VIRTIO_NET_F_CSUM): in print_feature_bits_all()
60 case BIT_ULL(VIRTIO_NET_F_GUEST_CSUM): in print_feature_bits_all()
63 case BIT_ULL(VIRTIO_NET_F_CTRL_GUEST_OFFLOADS): in print_feature_bits_all()
66 case BIT_ULL(VIRTIO_NET_F_MTU): in print_feature_bits_all()
69 case BIT_ULL(VIRTIO_NET_F_MAC): in print_feature_bits_all()
72 case BIT_ULL(VIRTIO_NET_F_GUEST_TSO4): in print_feature_bits_all()
75 case BIT_ULL(VIRTIO_NET_F_GUEST_TSO6): in print_feature_bits_all()
78 case BIT_ULL(VIRTIO_NET_F_GUEST_ECN): in print_feature_bits_all()
81 case BIT_ULL(VIRTIO_NET_F_GUEST_UFO): in print_feature_bits_all()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_flow.h14 (BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
15 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
17 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
18 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
20 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
21 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
23 (BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
24 BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
26 (BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
27 BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.h21 #define RPM_NIX0_RESET BIT_ULL(3)
22 #define RPMX_RX_TS_PREPEND BIT_ULL(22)
23 #define RPMX_TX_PTP_1S_SUPPORT BIT_ULL(17)
30 #define RPMX_MTI_PCS_LBK BIT_ULL(14)
36 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE BIT_ULL(29)
37 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE BIT_ULL(28)
38 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8)
39 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE BIT_ULL(19)
57 #define RPMX_CMR_RX_OVR_BP_EN(x) BIT_ULL((x) + 8)
58 #define RPMX_CMR_RX_OVR_BP_BP(x) BIT_ULL((x) + 4)
[all …]
H A Dcgx.h29 #define DATA_PKT_TX_EN BIT_ULL(53)
30 #define DATA_PKT_RX_EN BIT_ULL(54)
34 #define FW_CGX_INT BIT_ULL(1)
36 #define CGX_NIX0_RESET BIT_ULL(2)
37 #define CGX_NIX1_RESET BIT_ULL(3)
38 #define CGX_NSCI_DROP BIT_ULL(9)
45 #define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
46 #define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
47 #define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2)
48 #define CGX_DMAC_MCAST_MODE BIT_ULL(1)
[all …]
/openbmc/linux/drivers/firmware/efi/
H A Dcper-x86.c11 #define VALID_LAPIC_ID BIT_ULL(0)
12 #define VALID_CPUID_INFO BIT_ULL(1)
29 #define INFO_VALID_CHECK_INFO BIT_ULL(0)
30 #define INFO_VALID_TARGET_ID BIT_ULL(1)
31 #define INFO_VALID_REQUESTOR_ID BIT_ULL(2)
32 #define INFO_VALID_RESPONDER_ID BIT_ULL(3)
33 #define INFO_VALID_IP BIT_ULL(4)
35 #define CHECK_VALID_TRANS_TYPE BIT_ULL(0)
36 #define CHECK_VALID_OPERATION BIT_ULL(1)
37 #define CHECK_VALID_LEVEL BIT_ULL(2)
[all …]
/openbmc/linux/include/media/
H A Drc-map.h15 #define RC_PROTO_BIT_UNKNOWN BIT_ULL(RC_PROTO_UNKNOWN)
16 #define RC_PROTO_BIT_OTHER BIT_ULL(RC_PROTO_OTHER)
17 #define RC_PROTO_BIT_RC5 BIT_ULL(RC_PROTO_RC5)
18 #define RC_PROTO_BIT_RC5X_20 BIT_ULL(RC_PROTO_RC5X_20)
19 #define RC_PROTO_BIT_RC5_SZ BIT_ULL(RC_PROTO_RC5_SZ)
20 #define RC_PROTO_BIT_JVC BIT_ULL(RC_PROTO_JVC)
21 #define RC_PROTO_BIT_SONY12 BIT_ULL(RC_PROTO_SONY12)
22 #define RC_PROTO_BIT_SONY15 BIT_ULL(RC_PROTO_SONY15)
23 #define RC_PROTO_BIT_SONY20 BIT_ULL(RC_PROTO_SONY20)
24 #define RC_PROTO_BIT_NEC BIT_ULL(RC_PROTO_NEC)
[all …]
/openbmc/linux/tools/arch/x86/include/asm/
H A Dmsr-index.h70 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
232 #define LBR_INFO_MISPRED BIT_ULL(63)
233 #define LBR_INFO_IN_TX BIT_ULL(62)
234 #define LBR_INFO_ABORT BIT_ULL(61)
235 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
261 #define PERF_CAP_PEBS_TRAP BIT_ULL(6)
262 #define PERF_CAP_ARCH_REG BIT_ULL(7)
264 #define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
284 #define RTIT_CTL_NOTNT BIT_ULL(55)
342 #define MSR_IA32_PASID_VALID BIT_ULL(31)
[all …]
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_gem_gtt.h41 #define PIN_NOEVICT BIT_ULL(0)
42 #define PIN_NOSEARCH BIT_ULL(1)
43 #define PIN_NONBLOCK BIT_ULL(2)
44 #define PIN_MAPPABLE BIT_ULL(3)
45 #define PIN_ZONE_4G BIT_ULL(4)
46 #define PIN_HIGH BIT_ULL(5)
47 #define PIN_OFFSET_BIAS BIT_ULL(6)
48 #define PIN_OFFSET_FIXED BIT_ULL(7)
49 #define PIN_OFFSET_GUARD BIT_ULL(8)
50 #define PIN_VALIDATE BIT_ULL(9) /* validate placement only, no need to call unpin() */
[all …]
/openbmc/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2P.h160 #define HW_CAP_PLL BIT_ULL(0)
161 #define HW_CAP_DRAM BIT_ULL(1)
162 #define HW_CAP_PMMU BIT_ULL(2)
163 #define HW_CAP_CPU BIT_ULL(3)
164 #define HW_CAP_MSIX BIT_ULL(4)
166 #define HW_CAP_CPU_Q BIT_ULL(5)
169 #define HW_CAP_CLK_GATE BIT_ULL(6)
170 #define HW_CAP_KDMA BIT_ULL(7)
171 #define HW_CAP_SRAM_SCRAMBLER BIT_ULL(8)
173 #define HW_CAP_DCORE0_DMMU0 BIT_ULL(9)
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn66xx_regs.h367 #define CN6XXX_INTR_DMA0_FORCE BIT_ULL(32)
368 #define CN6XXX_INTR_DMA1_FORCE BIT_ULL(33)
369 #define CN6XXX_INTR_DMA0_COUNT BIT_ULL(34)
370 #define CN6XXX_INTR_DMA1_COUNT BIT_ULL(35)
371 #define CN6XXX_INTR_DMA0_TIME BIT_ULL(36)
372 #define CN6XXX_INTR_DMA1_TIME BIT_ULL(37)
373 #define CN6XXX_INTR_INSTR_DB_OF_ERR BIT_ULL(48)
374 #define CN6XXX_INTR_SLIST_DB_OF_ERR BIT_ULL(49)
375 #define CN6XXX_INTR_POUT_ERR BIT_ULL(50)
376 #define CN6XXX_INTR_PIN_BP_ERR BIT_ULL(51)
[all …]
H A Dcn23xx_pf_regs.h137 #define CN23XX_PKT_MAC_CTL_RINFO_TRS BIT_ULL(16)
186 #define CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32)
233 #define CN23XX_IN_DONE_CNTS_PI_INT BIT_ULL(62)
234 #define CN23XX_IN_DONE_CNTS_CINT_ENB BIT_ULL(48)
389 #define CN23XX_MSIX_ENTRY_VECTOR_CTL BIT_ULL(32)
425 #define CN23XX_INTR_PO_INT BIT_ULL(63)
426 #define CN23XX_INTR_PI_INT BIT_ULL(62)
427 #define CN23XX_INTR_MBOX_INT BIT_ULL(61)
428 #define CN23XX_INTR_RESEND BIT_ULL(60)
430 #define CN23XX_INTR_CINT_ENB BIT_ULL(48)
[all …]

12345678910>>...22