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Searched refs:ARCH_DMA_MINALIGN (Results 1 – 25 of 138) sorted by relevance

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/openbmc/u-boot/drivers/crypto/fsl/
H A Dfsl_blob.c33 if (!IS_ALIGNED((uintptr_t)key_mod, ARCH_DMA_MINALIGN) || in blob_decap()
34 !IS_ALIGNED((uintptr_t)src, ARCH_DMA_MINALIGN) || in blob_decap()
35 !IS_ALIGNED((uintptr_t)dst, ARCH_DMA_MINALIGN)) { in blob_decap()
47 size = ALIGN(16, ARCH_DMA_MINALIGN); in blob_decap()
51 size = ALIGN(BLOB_SIZE(len), ARCH_DMA_MINALIGN); in blob_decap()
61 size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN); in blob_decap()
70 size = ALIGN(len, ARCH_DMA_MINALIGN); in blob_decap()
98 if (!IS_ALIGNED((uintptr_t)key_mod, ARCH_DMA_MINALIGN) || in blob_encap()
99 !IS_ALIGNED((uintptr_t)src, ARCH_DMA_MINALIGN) || in blob_encap()
100 !IS_ALIGNED((uintptr_t)dst, ARCH_DMA_MINALIGN)) { in blob_encap()
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H A Dfsl_hash.c174 if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) || in caam_hash()
175 !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) { in caam_hash()
180 size = ALIGN(buf_len, ARCH_DMA_MINALIGN); in caam_hash()
188 size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN); in caam_hash()
193 size = ALIGN(driver_hash[algo].digestsize, ARCH_DMA_MINALIGN); in caam_hash()
H A Djr.c113 jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, in jr_init()
119 ARCH_DMA_MINALIGN); in jr_init()
121 (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size); in jr_init()
212 ~(ARCH_DMA_MINALIGN - 1); in jr_enqueue()
214 sizeof(struct jr_info), ARCH_DMA_MINALIGN); in jr_enqueue()
238 start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); in jr_enqueue()
240 sizeof(dma_addr_t), ARCH_DMA_MINALIGN); in jr_enqueue()
247 ~(ARCH_DMA_MINALIGN - 1); in jr_enqueue()
249 ARCH_DMA_MINALIGN); in jr_enqueue()
453 desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6); in instantiate_rng()
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/openbmc/u-boot/arch/arm/mach-omap2/
H A Dsec-common.c58 static uint32_t secure_rom_call_args[5] __aligned(ARCH_DMA_MINALIGN) __section(".data");
87 roundup(sizeof(secure_rom_call_args), ARCH_DMA_MINALIGN)); in secure_rom_call()
117 rounddown((u32)*image, ARCH_DMA_MINALIGN), in secure_boot_verify_image()
118 roundup((u32)*image + *size, ARCH_DMA_MINALIGN)); in secure_boot_verify_image()
159 rounddown((u32)*image, ARCH_DMA_MINALIGN), in secure_boot_verify_image()
160 roundup((u32)*image + *size, ARCH_DMA_MINALIGN)); in secure_boot_verify_image()
289 static struct ppa_tee_load_info tee_info __aligned(ARCH_DMA_MINALIGN);
338 rounddown((u32)loadptr, ARCH_DMA_MINALIGN), in secure_tee_install()
339 roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN)); in secure_tee_install()
342 roundup(sizeof(tee_info), ARCH_DMA_MINALIGN)); in secure_tee_install()
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/openbmc/u-boot/include/
H A Dmemalign.h79 ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad)
81 ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
94 DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
111 return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN)); in malloc_cache_aligned()
/openbmc/u-boot/arch/sandbox/include/asm/
H A Dcache.h18 #define ARCH_DMA_MINALIGN __BIGGEST_ALIGNMENT__ macro
20 #define ARCH_DMA_MINALIGN 16 macro
22 #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
/openbmc/u-boot/arch/sh/include/asm/
H A Dcache.h17 #define ARCH_DMA_MINALIGN 32 macro
25 #ifndef ARCH_DMA_MINALIGN
26 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES macro
/openbmc/u-boot/cmd/
H A Delf.c56 flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN), in load_elf64_image_phdr()
57 roundup(phdr->p_memsz, ARCH_DMA_MINALIGN)); in load_elf64_image_phdr()
119 flush_cache(rounddown(shdr->sh_addr, ARCH_DMA_MINALIGN), in load_elf64_image_shdr()
121 ARCH_DMA_MINALIGN) - in load_elf64_image_shdr()
122 rounddown(shdr->sh_addr, ARCH_DMA_MINALIGN)); in load_elf64_image_shdr()
171 flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN), in load_elf_image_phdr()
172 roundup(phdr->p_memsz, ARCH_DMA_MINALIGN)); in load_elf_image_phdr()
224 flush_cache(rounddown(shdr->sh_addr, ARCH_DMA_MINALIGN), in load_elf_image_shdr()
226 ARCH_DMA_MINALIGN) - in load_elf_image_shdr()
227 rounddown(shdr->sh_addr, ARCH_DMA_MINALIGN)); in load_elf_image_shdr()
/openbmc/u-boot/drivers/net/
H A Dfec_mxc.c63 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
66 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
70 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
71 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
334 size = roundup(dsize, ARCH_DMA_MINALIGN); in fec_rbd_init()
368 ARCH_DMA_MINALIGN); in fec_tbd_init()
481 ARCH_DMA_MINALIGN); in fec_open()
721 end = roundup(addr + length, ARCH_DMA_MINALIGN); in fecmxc_send()
722 addr &= ~(ARCH_DMA_MINALIGN - 1); in fecmxc_send()
745 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); in fecmxc_send()
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H A Dftgmac100.c328 end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN); in ftgmac100_start()
338 end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN); in ftgmac100_start()
402 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); in ftgmac100_free_pkt()
424 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); in ftgmac100_recv()
447 data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN); in ftgmac100_recv()
458 ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN); in ftgmac100_read_txdesc()
477 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); in BUILD_WAIT_FOR_BIT()
497 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); in BUILD_WAIT_FOR_BIT()
/openbmc/u-boot/common/
H A Dbouncebuf.c15 const ulong align_mask = ARCH_DMA_MINALIGN - 1; in addr_aligned()
39 state->len_aligned = roundup(len, ARCH_DMA_MINALIGN); in bounce_buffer_start()
43 state->bounce_buffer = memalign(ARCH_DMA_MINALIGN, in bounce_buffer_start()
/openbmc/u-boot/arch/microblaze/include/asm/
H A Dcache.h16 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE macro
18 #define ARCH_DMA_MINALIGN 16 macro
/openbmc/linux/arch/mips/include/asm/mach-ip32/
H A Dkmalloc.h7 #define ARCH_DMA_MINALIGN 32 macro
9 #define ARCH_DMA_MINALIGN 128 macro
/openbmc/u-boot/arch/riscv/include/asm/
H A Dcache.h19 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE macro
21 #define ARCH_DMA_MINALIGN 32 macro
/openbmc/u-boot/arch/mips/include/asm/
H A Dcache.h12 #define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) macro
19 #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
H A Dcacheops.h30 int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1; in icache_lock()
36 "n" (i * ARCH_DMA_MINALIGN), in icache_lock()
/openbmc/u-boot/arch/arc/include/asm/
H A Dcache.h17 #define ARCH_DMA_MINALIGN 128 macro
20 #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
/openbmc/u-boot/arch/arm/include/asm/
H A Ddma-mapping.h16 *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN)); in dma_alloc_coherent()
/openbmc/linux/arch/riscv/mm/
H A Ddma-noncoherent.c15 int dma_cache_alignment __ro_after_init = ARCH_DMA_MINALIGN;
134 WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN, in arch_setup_dma_ops()
138 ARCH_DMA_MINALIGN, riscv_cbom_block_size); in arch_setup_dma_ops()
/openbmc/u-boot/arch/nds32/include/asm/
H A Dcache.h58 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE macro
60 #define ARCH_DMA_MINALIGN 32 macro
/openbmc/linux/include/linux/
H A Dcache.h101 #ifdef ARCH_DMA_MINALIGN
104 #define ARCH_DMA_MINALIGN __alignof__(unsigned long long) macro
/openbmc/linux/drivers/usb/core/
H A Dbuffer.c39 if (ARCH_DMA_MINALIGN <= 32) in usb_init_pool_max()
41 else if (ARCH_DMA_MINALIGN <= 64) in usb_init_pool_max()
43 else if (ARCH_DMA_MINALIGN <= 128) in usb_init_pool_max()
/openbmc/u-boot/env/
H A Dsf.c101 saved_buffer = memalign(ARCH_DMA_MINALIGN, saved_size); in env_sf_save()
159 tmp_env1 = (env_t *)memalign(ARCH_DMA_MINALIGN, in env_sf_load()
161 tmp_env2 = (env_t *)memalign(ARCH_DMA_MINALIGN, in env_sf_load()
257 buf = (char *)memalign(ARCH_DMA_MINALIGN, CONFIG_ENV_SIZE); in env_sf_load()
/openbmc/u-boot/drivers/usb/host/
H A Dohci.h24 #if ARCH_DMA_MINALIGN > 16
25 #define ED_ALIGNMENT ARCH_DMA_MINALIGN
30 #if CONFIG_IS_ENABLED(DM_USB) && ARCH_DMA_MINALIGN > 32
31 #define TD_ALIGNMENT ARCH_DMA_MINALIGN
/openbmc/linux/arch/parisc/include/asm/
H A Dcache.h24 #define ARCH_DMA_MINALIGN 128 macro
26 #define ARCH_DMA_MINALIGN 32 macro

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