1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 200f892fcSMacpaul Lin /* 300f892fcSMacpaul Lin * Copyright (C) 2011 Andes Technology Corporation 400f892fcSMacpaul Lin * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 500f892fcSMacpaul Lin * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 600f892fcSMacpaul Lin */ 700f892fcSMacpaul Lin 800f892fcSMacpaul Lin #ifndef _ASM_CACHE_H 900f892fcSMacpaul Lin #define _ASM_CACHE_H 1000f892fcSMacpaul Lin 1100f892fcSMacpaul Lin /* cache */ 1200f892fcSMacpaul Lin int icache_status(void); 1300f892fcSMacpaul Lin void icache_enable(void); 1400f892fcSMacpaul Lin void icache_disable(void); 1500f892fcSMacpaul Lin int dcache_status(void); 1600f892fcSMacpaul Lin void dcache_enable(void); 1700f892fcSMacpaul Lin void dcache_disable(void); 18b841b6e9Srick void cache_flush(void); 1900f892fcSMacpaul Lin 2000f892fcSMacpaul Lin #define DEFINE_GET_SYS_REG(reg) \ 2100f892fcSMacpaul Lin static inline unsigned long GET_##reg(void) \ 2200f892fcSMacpaul Lin { \ 2300f892fcSMacpaul Lin unsigned long val; \ 2400f892fcSMacpaul Lin __asm__ volatile ( \ 2500f892fcSMacpaul Lin "mfsr %0, $"#reg : "=&r" (val) : : "memory" \ 2600f892fcSMacpaul Lin ); \ 2700f892fcSMacpaul Lin return val; \ 2800f892fcSMacpaul Lin } 2900f892fcSMacpaul Lin 3000f892fcSMacpaul Lin enum cache_t {ICACHE, DCACHE}; 3100f892fcSMacpaul Lin DEFINE_GET_SYS_REG(ICM_CFG); 3200f892fcSMacpaul Lin DEFINE_GET_SYS_REG(DCM_CFG); 33b841b6e9Srick /* I-cache sets (# of cache lines) per way */ 34b841b6e9Srick #define ICM_CFG_OFF_ISET 0 35b841b6e9Srick /* I-cache ways */ 36b841b6e9Srick #define ICM_CFG_OFF_IWAY 3 37b841b6e9Srick #define ICM_CFG_MSK_ISET (0x7 << ICM_CFG_OFF_ISET) 38b841b6e9Srick #define ICM_CFG_MSK_IWAY (0x7 << ICM_CFG_OFF_IWAY) 39b841b6e9Srick /* D-cache sets (# of cache lines) per way */ 40b841b6e9Srick #define DCM_CFG_OFF_DSET 0 41b841b6e9Srick /* D-cache ways */ 42b841b6e9Srick #define DCM_CFG_OFF_DWAY 3 43b841b6e9Srick #define DCM_CFG_MSK_DSET (0x7 << DCM_CFG_OFF_DSET) 44b841b6e9Srick #define DCM_CFG_MSK_DWAY (0x7 << DCM_CFG_OFF_DWAY) 45b841b6e9Srick /* I-cache line size */ 46b841b6e9Srick #define ICM_CFG_OFF_ISZ 6 4700f892fcSMacpaul Lin #define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) 48b841b6e9Srick /* D-cache line size */ 49b841b6e9Srick #define DCM_CFG_OFF_DSZ 6 5000f892fcSMacpaul Lin #define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) 5100f892fcSMacpaul Lin 52466e73b1SMacpaul Lin /* 53466e73b1SMacpaul Lin * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes. 54466e73b1SMacpaul Lin * We use that value for aligning DMA buffers unless the board config has 55466e73b1SMacpaul Lin * specified an alternate cache line size. 56466e73b1SMacpaul Lin */ 57466e73b1SMacpaul Lin #ifdef CONFIG_SYS_CACHELINE_SIZE 58466e73b1SMacpaul Lin #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 59466e73b1SMacpaul Lin #else 60466e73b1SMacpaul Lin #define ARCH_DMA_MINALIGN 32 61466e73b1SMacpaul Lin #endif 62466e73b1SMacpaul Lin 6300f892fcSMacpaul Lin #endif /* _ASM_CACHE_H */ 64