1819833afSPeter Tyser #ifndef __ASM_SH_CACHE_H 2819833afSPeter Tyser #define __ASM_SH_CACHE_H 3819833afSPeter Tyser 4*7d236662SMasahiro Yamada #if defined(CONFIG_CPU_SH4) 5819833afSPeter Tyser 6819833afSPeter Tyser #define L1_CACHE_BYTES 32 72482e3c8SAnton Staaf 8819833afSPeter Tyser struct __large_struct { unsigned long buf[100]; }; 9819833afSPeter Tyser #define __m(x) (*(struct __large_struct *)(x)) 10819833afSPeter Tyser 112482e3c8SAnton Staaf #else 122482e3c8SAnton Staaf 132482e3c8SAnton Staaf /* 142482e3c8SAnton Staaf * 32-bytes is the largest L1 data cache line size for SH the architecture. So 152482e3c8SAnton Staaf * it is a safe default for DMA alignment. 162482e3c8SAnton Staaf */ 172482e3c8SAnton Staaf #define ARCH_DMA_MINALIGN 32 182482e3c8SAnton Staaf 19*7d236662SMasahiro Yamada #endif /* CONFIG_CPU_SH4 */ 20819833afSPeter Tyser 212482e3c8SAnton Staaf /* 222482e3c8SAnton Staaf * Use the L1 data cache line size value for the minimum DMA buffer alignment 232482e3c8SAnton Staaf * on SH. 242482e3c8SAnton Staaf */ 252482e3c8SAnton Staaf #ifndef ARCH_DMA_MINALIGN 262482e3c8SAnton Staaf #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 272482e3c8SAnton Staaf #endif 282482e3c8SAnton Staaf 29819833afSPeter Tyser #endif /* __ASM_SH_CACHE_H */ 30