Searched hist:b40f734af9fdc47a0993f1f94f32d40a86f30587 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/u-boot/arch/arm/include/asm/arch-tegra114/ |
| H A D | sysctr.h | b40f734af9fdc47a0993f1f94f32d40a86f30587 Mon Apr 01 17:48:54 CDT 2013 Tom Warren <twarren@nvidia.com> Tegra114: Initialize System Counter (TSC) with osc frequency
T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
|
| H A D | tegra.h | diff b40f734af9fdc47a0993f1f94f32d40a86f30587 Mon Apr 01 17:48:54 CDT 2013 Tom Warren <twarren@nvidia.com> Tegra114: Initialize System Counter (TSC) with osc frequency
T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
|
| /openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | clock.h | diff b40f734af9fdc47a0993f1f94f32d40a86f30587 Mon Apr 01 17:48:54 CDT 2013 Tom Warren <twarren@nvidia.com> Tegra114: Initialize System Counter (TSC) with osc frequency
T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
|