1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 22fc65e28STom Warren /* 32fc65e28STom Warren * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 42fc65e28STom Warren */ 52fc65e28STom Warren 62fc65e28STom Warren #ifndef _TEGRA114_H_ 72fc65e28STom Warren #define _TEGRA114_H_ 82fc65e28STom Warren 92fc65e28STom Warren #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ 10b40f734aSTom Warren #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ 118c33ba7bSMarcel Ziswiler #define NV_PA_MC_BASE 0x70019000 122fc65e28STom Warren 132fc65e28STom Warren #include <asm/arch-tegra/tegra.h> 142fc65e28STom Warren 152fc65e28STom Warren #define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */ 162fc65e28STom Warren 172fc65e28STom Warren #undef NVBOOTINFOTABLE_BCTSIZE 182fc65e28STom Warren #undef NVBOOTINFOTABLE_BCTPTR 192fc65e28STom Warren #define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ 202fc65e28STom Warren #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ 212fc65e28STom Warren 222fc65e28STom Warren #define MAX_NUM_CPU 4 232fc65e28STom Warren 242fc65e28STom Warren #endif /* TEGRA114_H */ 25