1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2b40f734aSTom Warren /* 3b40f734aSTom Warren * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4b40f734aSTom Warren */ 5b40f734aSTom Warren 6b40f734aSTom Warren #ifndef _TEGRA114_SYSCTR_H_ 7b40f734aSTom Warren #define _TEGRA114_SYSCTR_H_ 8b40f734aSTom Warren 9b40f734aSTom Warren struct sysctr_ctlr { 10b40f734aSTom Warren u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ 11b40f734aSTom Warren u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ 12b40f734aSTom Warren u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ 13b40f734aSTom Warren u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ 14b40f734aSTom Warren u32 reserved1[4]; /* 0x10 - 0x1C */ 15b40f734aSTom Warren u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ 16b40f734aSTom Warren u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ 17b40f734aSTom Warren u32 reserved2[1002]; /* 0x28 - 0xFCC */ 18b40f734aSTom Warren u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ 19b40f734aSTom Warren }; 20b40f734aSTom Warren 21b40f734aSTom Warren #define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ 22b40f734aSTom Warren #define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ 23b40f734aSTom Warren 24b40f734aSTom Warren #endif /* _TEGRA114_SYSCTR_H_ */ 25