Searched hist:"0 c4e579aac30abd26818ebaec8e1b633eb9f3952" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/qemu/target/riscv/ |
| H A D | debug.c | diff 0c4e579aac30abd26818ebaec8e1b633eb9f3952 Tue Dec 19 06:32:44 CST 2023 Alvin Chang <alvinga@andestech.com> target/riscv: Implement optional CSR mcontext of debug Sdtrig extension
The debug Sdtrig extension defines an CSR "mcontext". This commit
implements its predicate and read/write operations into CSR table.
Its value is reset as 0 when the trigger module is reset.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231219123244.290935-1-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| H A D | cpu_bits.h | diff 0c4e579aac30abd26818ebaec8e1b633eb9f3952 Tue Dec 19 06:32:44 CST 2023 Alvin Chang <alvinga@andestech.com> target/riscv: Implement optional CSR mcontext of debug Sdtrig extension
The debug Sdtrig extension defines an CSR "mcontext". This commit
implements its predicate and read/write operations into CSR table.
Its value is reset as 0 when the trigger module is reset.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231219123244.290935-1-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| H A D | csr.c | diff 0c4e579aac30abd26818ebaec8e1b633eb9f3952 Tue Dec 19 06:32:44 CST 2023 Alvin Chang <alvinga@andestech.com> target/riscv: Implement optional CSR mcontext of debug Sdtrig extension
The debug Sdtrig extension defines an CSR "mcontext". This commit
implements its predicate and read/write operations into CSR table.
Its value is reset as 0 when the trigger module is reset.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231219123244.290935-1-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| H A D | cpu.h | diff 0c4e579aac30abd26818ebaec8e1b633eb9f3952 Tue Dec 19 06:32:44 CST 2023 Alvin Chang <alvinga@andestech.com> target/riscv: Implement optional CSR mcontext of debug Sdtrig extension
The debug Sdtrig extension defines an CSR "mcontext". This commit
implements its predicate and read/write operations into CSR table.
Its value is reset as 0 when the trigger module is reset.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231219123244.290935-1-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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