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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra124-xusb-padctl.txt1 Device tree binding for NVIDIA Tegra XUSB pad controller
4 NOTE: It turns out that this binding isn't an accurate description of the XUSB
7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
10 The Tegra XUSB pad controller manages a set of lanes, each of which can be
14 This document defines the device-specific binding for the XUSB pad controller.
16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
21 --------------------
22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3740-0002.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/sound/rt5640.h>
6 compatible = "nvidia,p3740-0002";
15 dai-format = "i2s";
16 remote-endpoint = <&rt5640_ep>;
26 bitclock-master;
27 frame-master;
36 rt5640: audio-codec@1c {
39 interrupt-parent = <&gpio>;
42 clock-names = "mclk";
[all …]
H A Dtegra234-p3768-0000.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 compatible = "nvidia,p3768-0000";
11 stdout-path = "serial0:115200n8";
23 vcc-supply = <&vdd_1v8_sys>;
24 address-width = <8>;
27 read-only;
36 assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
37 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
41 padctl@3520000 {
47 usb2-0 {
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dxusb-padctl.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
6 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
13 #include "../xusb-padctl-common.h"
15 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
55 "xusb",
94 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
95 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
96 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
97 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
[all …]
H A DMakefile2 # (C) Copyright 2013-2014
5 # SPDX-License-Identifier: GPL-2.0+
8 obj-$(CONFIG_SPL_BUILD) += cpu.o
10 obj-y += clock.o
11 obj-y += funcmux.o
12 obj-y += pinmux.o
13 obj-y += pmc.o
14 obj-y += xusb-padctl.o
15 obj-y += ../xusb-padctl-common.o
18 obj-$(CONFIG_ARMV7_NONSEC) += psci.o
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 exposed by the Tegra XUSB pad controller.
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
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H A Dnvidia,tegra-xudc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra XUSB device mode controller (XUDC)
14 - Nagarjuna Kristam <nkristam@nvidia.com>
15 - JC Kuo <jckuo@nvidia.com>
16 - Thierry Reding <treding@nvidia.com>
21 - enum:
22 - nvidia,tegra210-xudc # For Tegra210
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H A Dnvidia,tegra186-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 exposed by the Tegra XUSB pad controller.
18 const: nvidia,tegra186-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
[all …]
H A Dnvidia,tegra210-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 exposed by the Tegra XUSB pad controller.
18 const: nvidia,tegra210-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
[all …]
H A Dnvidia,tegra234-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra234-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 the Tegra XUSB pad controller. The xHCI controller controls up to eight
20 const: nvidia,tegra234-xusb
24 - description: xHCI host registers
25 - description: XUSB FPCI registers
[all …]
H A Dnvidia,tegra194-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 exposed by the Tegra XUSB pad controller.
18 const: nvidia,tegra194-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dxusb-padctl.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
6 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
13 #include "../xusb-padctl-common.h"
17 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
34 "xusb",
36 "pcie-x1",
37 "pcie-x4",
74 TEGRA210_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
75 TEGRA210_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
[all …]
H A DMakefile2 # (C) Copyright 2013-2015
5 # SPDX-License-Identifier: GPL-2.0+
8 obj-y += clock.o
9 obj-y += funcmux.o
10 obj-y += pinmux.o
11 obj-y += xusb-padctl.o
12 obj-y += ../xusb-padctl-common.o
/openbmc/linux/drivers/soc/tegra/fuse/
H A Dfuse-tegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
11 #include <linux/nvmem-consumer.h>
12 #include <linux/nvmem-provider.h>
44 if (WARN_ON(!fuse->base)) in tegra30_fuse_read_early()
47 return readl_relaxed(fuse->base + FUSE_BEGIN + offset); in tegra30_fuse_read_early()
55 err = pm_runtime_resume_and_get(fuse->dev); in tegra30_fuse_read()
59 value = readl_relaxed(fuse->base + FUSE_BEGIN + offset); in tegra30_fuse_read()
61 pm_runtime_put(fuse->dev); in tegra30_fuse_read()
90 fuse->read_early = tegra30_fuse_read_early; in tegra30_fuse_init()
[all …]
/openbmc/linux/drivers/phy/tegra/
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
13 #include <linux/phy/tegra/xusb.h>
22 #include "xusb.h"
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
[all …]
H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
18 #include "xusb.h"
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
31 /* XUSB PADCTL registers */
121 /* XUSB AO registers */
274 /* padctl context */
280 writel(value, priv->ao_regs + offset); in ao_writel()
285 return readl(priv->ao_regs + offset); in ao_readl()
289 to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl) in to_tegra186_xusb_padctl() argument
[all …]
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include "xusb.h"
220 to_tegra124_xusb_padctl(struct tegra_xusb_padctl *padctl) in to_tegra124_xusb_padctl() argument
222 return container_of(padctl, struct tegra124_xusb_padctl, base); in to_tegra124_xusb_padctl()
225 static int tegra124_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) in tegra124_xusb_padctl_enable() argument
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
234 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
236 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
240 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dxusb-padctl-common.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
6 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
11 #include "xusb-padctl-common.h"
17 if (phy && phy->ops && phy->ops->prepare) in tegra_xusb_phy_prepare()
18 return phy->ops->prepare(phy); in tegra_xusb_phy_prepare()
20 return phy ? -ENOSYS : -EINVAL; in tegra_xusb_phy_prepare()
25 if (phy && phy->ops && phy->ops->enable) in tegra_xusb_phy_enable()
26 return phy->ops->enable(phy); in tegra_xusb_phy_enable()
28 return phy ? -ENOSYS : -EINVAL; in tegra_xusb_phy_enable()
[all …]
H A Dxusb-padctl-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
14 #include <asm/arch-tegra/xusb-padctl.h>
39 struct tegra_xusb_padctl *padctl; member
85 extern struct tegra_xusb_padctl padctl;
87 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, in padctl_readl() argument
90 return readl(padctl->regs.start + offset); in padctl_readl()
93 static inline void padctl_writel(struct tegra_xusb_padctl *padctl, in padctl_writel() argument
96 writel(value, padctl->regs.start + offset); in padctl_writel()
/openbmc/linux/drivers/usb/host/
H A Dxhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
11 #include <linux/dma-mapping.h>
20 #include <linux/phy/tegra/xusb.h>
275 struct tegra_xusb_padctl *padctl; member
321 return readl(tegra->fpci_base + offset); in fpci_readl()
327 writel(value, tegra->fpci_base + offset); in fpci_writel()
332 return readl(tegra->ipfs_base + offset); in ipfs_readl()
338 writel(value, tegra->ipfs_base + offset); in ipfs_writel()
343 return readl(tegra->bar2_base + offset); in bar2_readl()
[all …]
/openbmc/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra-xusb.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
23 #include "../pinctrl-utils.h"
96 static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value, in padctl_writel() argument
99 writel(value, padctl->regs + offset); in padctl_writel()
102 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, in padctl_readl() argument
105 return readl(padctl->regs + offset); in padctl_readl()
110 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); in tegra_xusb_padctl_get_groups_count() local
112 return padctl->soc->num_pins; in tegra_xusb_padctl_get_groups_count()
118 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); in tegra_xusb_padctl_get_group_name() local
[all …]

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