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Searched full:tx_clk (Results 1 – 25 of 47) sorted by relevance

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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-sunxi.c23 struct clk *tx_clk; member
48 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); in sun7i_gmac_init()
49 clk_prepare_enable(gmac->tx_clk); in sun7i_gmac_init()
52 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE); in sun7i_gmac_init()
53 ret = clk_prepare(gmac->tx_clk); in sun7i_gmac_init()
66 clk_disable(gmac->tx_clk); in sun7i_gmac_exit()
69 clk_unprepare(gmac->tx_clk); in sun7i_gmac_exit()
84 clk_disable(gmac->tx_clk); in sun7i_fix_speed()
87 clk_unprepare(gmac->tx_clk); in sun7i_fix_speed()
90 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); in sun7i_fix_speed()
[all …]
H A Ddwmac-intel-plat.c20 struct clk *tx_clk; member
37 rate = clk_get_rate(dwmac->tx_clk); in kmb_eth_fix_mac_speed()
57 ret = clk_set_rate(dwmac->tx_clk, rate); in kmb_eth_fix_mac_speed()
99 dwmac->tx_clk = NULL; in intel_eth_plat_probe()
110 dwmac->tx_clk = devm_clk_get(&pdev->dev, "tx_clk"); in intel_eth_plat_probe()
111 if (IS_ERR(dwmac->tx_clk)) in intel_eth_plat_probe()
112 return PTR_ERR(dwmac->tx_clk); in intel_eth_plat_probe()
114 ret = clk_prepare_enable(dwmac->tx_clk); in intel_eth_plat_probe()
117 "Failed to enable tx_clk\n"); in intel_eth_plat_probe()
122 rate = clk_get_rate(dwmac->tx_clk); in intel_eth_plat_probe()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dls1012a_serdes.c22 {0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
23 {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
24 {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
/openbmc/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-rx.c71 struct clk *tx_clk; member
129 clk_set_rate(dphy->tx_clk, 19800000); in stf_dphy_power_on()
180 dphy->tx_clk = devm_clk_get(&pdev->dev, "tx"); in stf_dphy_probe()
181 if (IS_ERR(dphy->tx_clk)) in stf_dphy_probe()
182 return PTR_ERR(dphy->tx_clk); in stf_dphy_probe()
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-clk-ccf.dtsi193 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
198 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
203 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
208 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
H A Dzynq-7000.dtsi222 clock-names = "pclk", "hclk", "tx_clk";
233 clock-names = "pclk", "hclk", "tx_clk";
H A Dsocfpga_arria10_socdk.dtsi76 * for TX_CLK on Arria 10.
H A Dzynqmp.dtsi513 clock-names = "pclk", "hclk", "tx_clk";
526 clock-names = "pclk", "hclk", "tx_clk";
539 clock-names = "pclk", "hclk", "tx_clk";
552 clock-names = "pclk", "hclk", "tx_clk";
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml82 - const: tx_clk
182 clock-names = "pclk", "hclk", "tx_clk";
210 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
H A Dintel,dwmac-plat.yaml42 - const: tx_clk
110 clock-names = "stmmaceth", "ptp_ref", "tx_clk";
H A Dqcom-emac.txt44 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
93 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
/openbmc/u-boot/drivers/video/
H A Dssd2828.c123 * and "TX_CLK Timing Characteristics" tables in the SSD2828 datasheet, in soft_spi_xfer_24bit_3wire()
124 * the lowest possible 'tx_clk' clock frequency is 8MHz, and SPI runs in soft_spi_xfer_24bit_3wire()
127 * need to be longer (up to 16 'tx_clk' cycles, or 2 microseconds in in soft_spi_xfer_24bit_3wire()
376 * Pick the reference clock for PLL. If we know the exact 'tx_clk' in ssd2828_init()
H A Dssd2828.h45 * The SSD2828 has its own dedicated clock source 'tx_clk' (connected
49 * 8MHz - 30MHz range (see "TX_CLK Timing" section). It can be also
H A DKconfig333 int "SSD2828 TX_CLK frequency (in MHz)"
342 parallel LCD interface instead of TX_CLK as the PLL clock source.
/openbmc/linux/drivers/dma/xilinx/
H A Dxilinx_dma.c477 struct clk **tx_clk, struct clk **txs_clk,
494 * @tx_clk: DMA mm2s clock
513 struct clk *tx_clk; member
2616 struct clk **tx_clk, struct clk **rx_clk, in axidma_clk_init() argument
2627 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); in axidma_clk_init()
2628 if (IS_ERR(*tx_clk)) in axidma_clk_init()
2629 *tx_clk = NULL; in axidma_clk_init()
2645 err = clk_prepare_enable(*tx_clk); in axidma_clk_init()
2647 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); in axidma_clk_init()
2668 clk_disable_unprepare(*tx_clk); in axidma_clk_init()
[all …]
/openbmc/linux/drivers/net/ethernet/cadence/
H A Dmacb_main.c526 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG)) in macb_set_tx_clk()
547 rate_rounded = clk_round_rate(bp->tx_clk, rate); in macb_set_tx_clk()
561 if (clk_set_rate(bp->tx_clk, rate_rounded)) in macb_set_tx_clk()
562 netdev_err(bp->dev, "adjusting tx_clk failed.\n"); in macb_set_tx_clk()
3967 static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk, in macb_clks_disable()
3975 { .clk = tx_clk }, in macb_clk_init() argument
3982 struct clk **hclk, struct clk **tx_clk, in macb_clk_init()
4007 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk"); in macb_clk_init()
4008 if (IS_ERR(*tx_clk)) in macb_clk_init()
3960 macb_clks_disable(struct clk * pclk,struct clk * hclk,struct clk * tx_clk,struct clk * rx_clk,struct clk * tsu_clk) macb_clks_disable() argument
4553 at91ether_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk) at91ether_clk_init() argument
4650 fu540_c000_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk) fu540_c000_clk_init() argument
4959 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL; macb_probe() local
[all...]
/openbmc/u-boot/arch/arm/cpu/armv7/stv0991/
H A Dclock.c32 /* Clock selection for ethernet tx_clk & rx_clk*/ in clock_setup()
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dfsl_serdes.h174 TX_CLK, enumerator
/openbmc/linux/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c303 /* Per MII spec, the PHY (which is us) drives the TX_CLK pin */ in sja1105_mii_clocking_setup()
411 pad_mii_tx.clk_os = 3; /* TX_CLK output stage */ in sja1105_rgmii_cfg_pad_tx_config()
412 pad_mii_tx.clk_ih = 0; /* TX_CLK input hysteresis (default) */ in sja1105_rgmii_cfg_pad_tx_config()
413 pad_mii_tx.clk_ipud = 2; /* TX_CLK input stage (default) */ in sja1105_rgmii_cfg_pad_tx_config()
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc832x_rdb.dts180 3 23 2 0 1 0 /* TX_CLK (CLK3) */
200 3 24 2 0 1 0 /* TX_CLK (CLK10) */
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10_socdk.dtsi75 * for TX_CLK on Arria 10.
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi586 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
602 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
618 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
634 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi253 clock-names = "pclk", "hclk", "tx_clk";
264 clock-names = "pclk", "hclk", "tx_clk";
/openbmc/linux/drivers/net/ethernet/intel/e1000/
H A De1000_ethtool.c1120 /* Because we reset the PHY above, we need to re-force TX_CLK in the in e1000_phy_reset_clk_and_crs()
1166 /* Have to setup TX_CLK and TX_CRS after software reset */ in e1000_nonintegrated_phy_loopback()
1174 /* Have to setup TX_CLK and TX_CRS after software reset */ in e1000_nonintegrated_phy_loopback()
1185 /* Setup TX_CLK and TX_CRS one more time. */ in e1000_nonintegrated_phy_loopback()
/openbmc/linux/drivers/net/phy/
H A Dmicrel.c921 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
925 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
1007 u16 rx, tx, rx_clk, tx_clk; in ksz9031_config_rgmii_delay() local
1013 tx_clk = TX_CLK_ND; in ksz9031_config_rgmii_delay()
1019 tx_clk = TX_CLK_ID; in ksz9031_config_rgmii_delay()
1025 tx_clk = TX_CLK_ND; in ksz9031_config_rgmii_delay()
1031 tx_clk = TX_CLK_ID; in ksz9031_config_rgmii_delay()
1062 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) | in ksz9031_config_rgmii_delay()

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