xref: /openbmc/linux/drivers/net/dsa/sja1105/sja1105_clocking.c (revision 03ab8e6297acd1bc0eedaa050e2a1635c576fd11)
18aa9ebccSVladimir Oltean // SPDX-License-Identifier: BSD-3-Clause
23c9cfb52SVladimir Oltean /* Copyright 2016-2018 NXP
38aa9ebccSVladimir Oltean  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
48aa9ebccSVladimir Oltean  */
58aa9ebccSVladimir Oltean #include <linux/packing.h>
68aa9ebccSVladimir Oltean #include "sja1105.h"
78aa9ebccSVladimir Oltean 
88aa9ebccSVladimir Oltean #define SJA1105_SIZE_CGU_CMD	4
9cb5a82d2SVladimir Oltean #define SJA1110_BASE_MCSS_CLK	SJA1110_CGU_ADDR(0x70)
103e77e59bSVladimir Oltean #define SJA1110_BASE_TIMER_CLK	SJA1110_CGU_ADDR(0x74)
118aa9ebccSVladimir Oltean 
12135e3018SVladimir Oltean /* Common structure for CFG_PAD_MIIx_RX and CFG_PAD_MIIx_TX */
13135e3018SVladimir Oltean struct sja1105_cfg_pad_mii {
148aa9ebccSVladimir Oltean 	u64 d32_os;
15135e3018SVladimir Oltean 	u64 d32_ih;
168aa9ebccSVladimir Oltean 	u64 d32_ipud;
17135e3018SVladimir Oltean 	u64 d10_ih;
188aa9ebccSVladimir Oltean 	u64 d10_os;
198aa9ebccSVladimir Oltean 	u64 d10_ipud;
208aa9ebccSVladimir Oltean 	u64 ctrl_os;
21135e3018SVladimir Oltean 	u64 ctrl_ih;
228aa9ebccSVladimir Oltean 	u64 ctrl_ipud;
238aa9ebccSVladimir Oltean 	u64 clk_os;
248aa9ebccSVladimir Oltean 	u64 clk_ih;
258aa9ebccSVladimir Oltean 	u64 clk_ipud;
268aa9ebccSVladimir Oltean };
278aa9ebccSVladimir Oltean 
28c05ec3d4SVladimir Oltean struct sja1105_cfg_pad_mii_id {
29c05ec3d4SVladimir Oltean 	u64 rxc_stable_ovr;
30c05ec3d4SVladimir Oltean 	u64 rxc_delay;
31c05ec3d4SVladimir Oltean 	u64 rxc_bypass;
32c05ec3d4SVladimir Oltean 	u64 rxc_pd;
33c05ec3d4SVladimir Oltean 	u64 txc_stable_ovr;
34c05ec3d4SVladimir Oltean 	u64 txc_delay;
35c05ec3d4SVladimir Oltean 	u64 txc_bypass;
36c05ec3d4SVladimir Oltean 	u64 txc_pd;
37c05ec3d4SVladimir Oltean };
38c05ec3d4SVladimir Oltean 
398aa9ebccSVladimir Oltean /* UM10944 Table 82.
408aa9ebccSVladimir Oltean  * IDIV_0_C to IDIV_4_C control registers
418aa9ebccSVladimir Oltean  * (addr. 10000Bh to 10000Fh)
428aa9ebccSVladimir Oltean  */
438aa9ebccSVladimir Oltean struct sja1105_cgu_idiv {
448aa9ebccSVladimir Oltean 	u64 clksrc;
458aa9ebccSVladimir Oltean 	u64 autoblock;
468aa9ebccSVladimir Oltean 	u64 idiv;
478aa9ebccSVladimir Oltean 	u64 pd;
488aa9ebccSVladimir Oltean };
498aa9ebccSVladimir Oltean 
508aa9ebccSVladimir Oltean /* PLL_1_C control register
518aa9ebccSVladimir Oltean  *
528aa9ebccSVladimir Oltean  * SJA1105 E/T: UM10944 Table 81 (address 10000Ah)
538aa9ebccSVladimir Oltean  * SJA1105 P/Q/R/S: UM11040 Table 116 (address 10000Ah)
548aa9ebccSVladimir Oltean  */
558aa9ebccSVladimir Oltean struct sja1105_cgu_pll_ctrl {
568aa9ebccSVladimir Oltean 	u64 pllclksrc;
578aa9ebccSVladimir Oltean 	u64 msel;
588aa9ebccSVladimir Oltean 	u64 autoblock;
598aa9ebccSVladimir Oltean 	u64 psel;
608aa9ebccSVladimir Oltean 	u64 direct;
618aa9ebccSVladimir Oltean 	u64 fbsel;
628aa9ebccSVladimir Oltean 	u64 bypass;
638aa9ebccSVladimir Oltean 	u64 pd;
648aa9ebccSVladimir Oltean };
658aa9ebccSVladimir Oltean 
663e77e59bSVladimir Oltean struct sja1110_cgu_outclk {
673e77e59bSVladimir Oltean 	u64 clksrc;
683e77e59bSVladimir Oltean 	u64 autoblock;
693e77e59bSVladimir Oltean 	u64 pd;
703e77e59bSVladimir Oltean };
713e77e59bSVladimir Oltean 
728aa9ebccSVladimir Oltean enum {
738aa9ebccSVladimir Oltean 	CLKSRC_MII0_TX_CLK	= 0x00,
748aa9ebccSVladimir Oltean 	CLKSRC_MII0_RX_CLK	= 0x01,
758aa9ebccSVladimir Oltean 	CLKSRC_MII1_TX_CLK	= 0x02,
768aa9ebccSVladimir Oltean 	CLKSRC_MII1_RX_CLK	= 0x03,
778aa9ebccSVladimir Oltean 	CLKSRC_MII2_TX_CLK	= 0x04,
788aa9ebccSVladimir Oltean 	CLKSRC_MII2_RX_CLK	= 0x05,
798aa9ebccSVladimir Oltean 	CLKSRC_MII3_TX_CLK	= 0x06,
808aa9ebccSVladimir Oltean 	CLKSRC_MII3_RX_CLK	= 0x07,
818aa9ebccSVladimir Oltean 	CLKSRC_MII4_TX_CLK	= 0x08,
828aa9ebccSVladimir Oltean 	CLKSRC_MII4_RX_CLK	= 0x09,
838aa9ebccSVladimir Oltean 	CLKSRC_PLL0		= 0x0B,
848aa9ebccSVladimir Oltean 	CLKSRC_PLL1		= 0x0E,
858aa9ebccSVladimir Oltean 	CLKSRC_IDIV0		= 0x11,
868aa9ebccSVladimir Oltean 	CLKSRC_IDIV1		= 0x12,
878aa9ebccSVladimir Oltean 	CLKSRC_IDIV2		= 0x13,
888aa9ebccSVladimir Oltean 	CLKSRC_IDIV3		= 0x14,
898aa9ebccSVladimir Oltean 	CLKSRC_IDIV4		= 0x15,
908aa9ebccSVladimir Oltean };
918aa9ebccSVladimir Oltean 
928aa9ebccSVladimir Oltean /* UM10944 Table 83.
938aa9ebccSVladimir Oltean  * MIIx clock control registers 1 to 30
948aa9ebccSVladimir Oltean  * (addresses 100013h to 100035h)
958aa9ebccSVladimir Oltean  */
968aa9ebccSVladimir Oltean struct sja1105_cgu_mii_ctrl {
978aa9ebccSVladimir Oltean 	u64 clksrc;
988aa9ebccSVladimir Oltean 	u64 autoblock;
998aa9ebccSVladimir Oltean 	u64 pd;
1008aa9ebccSVladimir Oltean };
1018aa9ebccSVladimir Oltean 
sja1105_cgu_idiv_packing(void * buf,struct sja1105_cgu_idiv * idiv,enum packing_op op)1028aa9ebccSVladimir Oltean static void sja1105_cgu_idiv_packing(void *buf, struct sja1105_cgu_idiv *idiv,
1038aa9ebccSVladimir Oltean 				     enum packing_op op)
1048aa9ebccSVladimir Oltean {
1058aa9ebccSVladimir Oltean 	const int size = 4;
1068aa9ebccSVladimir Oltean 
1078aa9ebccSVladimir Oltean 	sja1105_packing(buf, &idiv->clksrc,    28, 24, size, op);
1088aa9ebccSVladimir Oltean 	sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op);
1098aa9ebccSVladimir Oltean 	sja1105_packing(buf, &idiv->idiv,       5,  2, size, op);
1108aa9ebccSVladimir Oltean 	sja1105_packing(buf, &idiv->pd,         0,  0, size, op);
1118aa9ebccSVladimir Oltean }
1128aa9ebccSVladimir Oltean 
sja1105_cgu_idiv_config(struct sja1105_private * priv,int port,bool enabled,int factor)1138aa9ebccSVladimir Oltean static int sja1105_cgu_idiv_config(struct sja1105_private *priv, int port,
1148aa9ebccSVladimir Oltean 				   bool enabled, int factor)
1158aa9ebccSVladimir Oltean {
1168aa9ebccSVladimir Oltean 	const struct sja1105_regs *regs = priv->info->regs;
1178aa9ebccSVladimir Oltean 	struct device *dev = priv->ds->dev;
1188aa9ebccSVladimir Oltean 	struct sja1105_cgu_idiv idiv;
1198aa9ebccSVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
1208aa9ebccSVladimir Oltean 
121c5037678SVladimir Oltean 	if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR)
122c5037678SVladimir Oltean 		return 0;
123c5037678SVladimir Oltean 
1248aa9ebccSVladimir Oltean 	if (enabled && factor != 1 && factor != 10) {
1258aa9ebccSVladimir Oltean 		dev_err(dev, "idiv factor must be 1 or 10\n");
1268aa9ebccSVladimir Oltean 		return -ERANGE;
1278aa9ebccSVladimir Oltean 	}
1288aa9ebccSVladimir Oltean 
1298aa9ebccSVladimir Oltean 	/* Payload for packed_buf */
1308aa9ebccSVladimir Oltean 	idiv.clksrc    = 0x0A;            /* 25MHz */
1318aa9ebccSVladimir Oltean 	idiv.autoblock = 1;               /* Block clk automatically */
1328aa9ebccSVladimir Oltean 	idiv.idiv      = factor - 1;      /* Divide by 1 or 10 */
1338aa9ebccSVladimir Oltean 	idiv.pd        = enabled ? 0 : 1; /* Power down? */
1348aa9ebccSVladimir Oltean 	sja1105_cgu_idiv_packing(packed_buf, &idiv, PACK);
1358aa9ebccSVladimir Oltean 
1361bd44870SVladimir Oltean 	return sja1105_xfer_buf(priv, SPI_WRITE, regs->cgu_idiv[port],
1371bd44870SVladimir Oltean 				packed_buf, SJA1105_SIZE_CGU_CMD);
1388aa9ebccSVladimir Oltean }
1398aa9ebccSVladimir Oltean 
1408aa9ebccSVladimir Oltean static void
sja1105_cgu_mii_control_packing(void * buf,struct sja1105_cgu_mii_ctrl * cmd,enum packing_op op)1418aa9ebccSVladimir Oltean sja1105_cgu_mii_control_packing(void *buf, struct sja1105_cgu_mii_ctrl *cmd,
1428aa9ebccSVladimir Oltean 				enum packing_op op)
1438aa9ebccSVladimir Oltean {
1448aa9ebccSVladimir Oltean 	const int size = 4;
1458aa9ebccSVladimir Oltean 
1468aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->clksrc,    28, 24, size, op);
1478aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op);
1488aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->pd,         0,  0, size, op);
1498aa9ebccSVladimir Oltean }
1508aa9ebccSVladimir Oltean 
sja1105_cgu_mii_tx_clk_config(struct sja1105_private * priv,int port,sja1105_mii_role_t role)1518aa9ebccSVladimir Oltean static int sja1105_cgu_mii_tx_clk_config(struct sja1105_private *priv,
1528aa9ebccSVladimir Oltean 					 int port, sja1105_mii_role_t role)
1538aa9ebccSVladimir Oltean {
1548aa9ebccSVladimir Oltean 	const struct sja1105_regs *regs = priv->info->regs;
1558aa9ebccSVladimir Oltean 	struct sja1105_cgu_mii_ctrl mii_tx_clk;
1568aa9ebccSVladimir Oltean 	const int mac_clk_sources[] = {
1578aa9ebccSVladimir Oltean 		CLKSRC_MII0_TX_CLK,
1588aa9ebccSVladimir Oltean 		CLKSRC_MII1_TX_CLK,
1598aa9ebccSVladimir Oltean 		CLKSRC_MII2_TX_CLK,
1608aa9ebccSVladimir Oltean 		CLKSRC_MII3_TX_CLK,
1618aa9ebccSVladimir Oltean 		CLKSRC_MII4_TX_CLK,
1628aa9ebccSVladimir Oltean 	};
1638aa9ebccSVladimir Oltean 	const int phy_clk_sources[] = {
1648aa9ebccSVladimir Oltean 		CLKSRC_IDIV0,
1658aa9ebccSVladimir Oltean 		CLKSRC_IDIV1,
1668aa9ebccSVladimir Oltean 		CLKSRC_IDIV2,
1678aa9ebccSVladimir Oltean 		CLKSRC_IDIV3,
1688aa9ebccSVladimir Oltean 		CLKSRC_IDIV4,
1698aa9ebccSVladimir Oltean 	};
1708aa9ebccSVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
1718aa9ebccSVladimir Oltean 	int clksrc;
1728aa9ebccSVladimir Oltean 
173c5037678SVladimir Oltean 	if (regs->mii_tx_clk[port] == SJA1105_RSV_ADDR)
174c5037678SVladimir Oltean 		return 0;
175c5037678SVladimir Oltean 
1768aa9ebccSVladimir Oltean 	if (role == XMII_MAC)
1778aa9ebccSVladimir Oltean 		clksrc = mac_clk_sources[port];
1788aa9ebccSVladimir Oltean 	else
1798aa9ebccSVladimir Oltean 		clksrc = phy_clk_sources[port];
1808aa9ebccSVladimir Oltean 
1818aa9ebccSVladimir Oltean 	/* Payload for packed_buf */
1828aa9ebccSVladimir Oltean 	mii_tx_clk.clksrc    = clksrc;
1838aa9ebccSVladimir Oltean 	mii_tx_clk.autoblock = 1;  /* Autoblock clk while changing clksrc */
1848aa9ebccSVladimir Oltean 	mii_tx_clk.pd        = 0;  /* Power Down off => enabled */
1858aa9ebccSVladimir Oltean 	sja1105_cgu_mii_control_packing(packed_buf, &mii_tx_clk, PACK);
1868aa9ebccSVladimir Oltean 
1871bd44870SVladimir Oltean 	return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_tx_clk[port],
1881bd44870SVladimir Oltean 				packed_buf, SJA1105_SIZE_CGU_CMD);
1898aa9ebccSVladimir Oltean }
1908aa9ebccSVladimir Oltean 
1918aa9ebccSVladimir Oltean static int
sja1105_cgu_mii_rx_clk_config(struct sja1105_private * priv,int port)1928aa9ebccSVladimir Oltean sja1105_cgu_mii_rx_clk_config(struct sja1105_private *priv, int port)
1938aa9ebccSVladimir Oltean {
1948aa9ebccSVladimir Oltean 	const struct sja1105_regs *regs = priv->info->regs;
1958aa9ebccSVladimir Oltean 	struct sja1105_cgu_mii_ctrl mii_rx_clk;
1968aa9ebccSVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
1978aa9ebccSVladimir Oltean 	const int clk_sources[] = {
1988aa9ebccSVladimir Oltean 		CLKSRC_MII0_RX_CLK,
1998aa9ebccSVladimir Oltean 		CLKSRC_MII1_RX_CLK,
2008aa9ebccSVladimir Oltean 		CLKSRC_MII2_RX_CLK,
2018aa9ebccSVladimir Oltean 		CLKSRC_MII3_RX_CLK,
2028aa9ebccSVladimir Oltean 		CLKSRC_MII4_RX_CLK,
2038aa9ebccSVladimir Oltean 	};
2048aa9ebccSVladimir Oltean 
205c5037678SVladimir Oltean 	if (regs->mii_rx_clk[port] == SJA1105_RSV_ADDR)
206c5037678SVladimir Oltean 		return 0;
207c5037678SVladimir Oltean 
2088aa9ebccSVladimir Oltean 	/* Payload for packed_buf */
2098aa9ebccSVladimir Oltean 	mii_rx_clk.clksrc    = clk_sources[port];
2108aa9ebccSVladimir Oltean 	mii_rx_clk.autoblock = 1;  /* Autoblock clk while changing clksrc */
2118aa9ebccSVladimir Oltean 	mii_rx_clk.pd        = 0;  /* Power Down off => enabled */
2128aa9ebccSVladimir Oltean 	sja1105_cgu_mii_control_packing(packed_buf, &mii_rx_clk, PACK);
2138aa9ebccSVladimir Oltean 
2141bd44870SVladimir Oltean 	return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_rx_clk[port],
2151bd44870SVladimir Oltean 				packed_buf, SJA1105_SIZE_CGU_CMD);
2168aa9ebccSVladimir Oltean }
2178aa9ebccSVladimir Oltean 
2188aa9ebccSVladimir Oltean static int
sja1105_cgu_mii_ext_tx_clk_config(struct sja1105_private * priv,int port)2198aa9ebccSVladimir Oltean sja1105_cgu_mii_ext_tx_clk_config(struct sja1105_private *priv, int port)
2208aa9ebccSVladimir Oltean {
2218aa9ebccSVladimir Oltean 	const struct sja1105_regs *regs = priv->info->regs;
2228aa9ebccSVladimir Oltean 	struct sja1105_cgu_mii_ctrl mii_ext_tx_clk;
2238aa9ebccSVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
2248aa9ebccSVladimir Oltean 	const int clk_sources[] = {
2258aa9ebccSVladimir Oltean 		CLKSRC_IDIV0,
2268aa9ebccSVladimir Oltean 		CLKSRC_IDIV1,
2278aa9ebccSVladimir Oltean 		CLKSRC_IDIV2,
2288aa9ebccSVladimir Oltean 		CLKSRC_IDIV3,
2298aa9ebccSVladimir Oltean 		CLKSRC_IDIV4,
2308aa9ebccSVladimir Oltean 	};
2318aa9ebccSVladimir Oltean 
232c5037678SVladimir Oltean 	if (regs->mii_ext_tx_clk[port] == SJA1105_RSV_ADDR)
233c5037678SVladimir Oltean 		return 0;
234c5037678SVladimir Oltean 
2358aa9ebccSVladimir Oltean 	/* Payload for packed_buf */
2368aa9ebccSVladimir Oltean 	mii_ext_tx_clk.clksrc    = clk_sources[port];
2378aa9ebccSVladimir Oltean 	mii_ext_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
2388aa9ebccSVladimir Oltean 	mii_ext_tx_clk.pd        = 0; /* Power Down off => enabled */
2398aa9ebccSVladimir Oltean 	sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_tx_clk, PACK);
2408aa9ebccSVladimir Oltean 
2411bd44870SVladimir Oltean 	return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_tx_clk[port],
2428aa9ebccSVladimir Oltean 				packed_buf, SJA1105_SIZE_CGU_CMD);
2438aa9ebccSVladimir Oltean }
2448aa9ebccSVladimir Oltean 
2458aa9ebccSVladimir Oltean static int
sja1105_cgu_mii_ext_rx_clk_config(struct sja1105_private * priv,int port)2468aa9ebccSVladimir Oltean sja1105_cgu_mii_ext_rx_clk_config(struct sja1105_private *priv, int port)
2478aa9ebccSVladimir Oltean {
2488aa9ebccSVladimir Oltean 	const struct sja1105_regs *regs = priv->info->regs;
2498aa9ebccSVladimir Oltean 	struct sja1105_cgu_mii_ctrl mii_ext_rx_clk;
2508aa9ebccSVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
2518aa9ebccSVladimir Oltean 	const int clk_sources[] = {
2528aa9ebccSVladimir Oltean 		CLKSRC_IDIV0,
2538aa9ebccSVladimir Oltean 		CLKSRC_IDIV1,
2548aa9ebccSVladimir Oltean 		CLKSRC_IDIV2,
2558aa9ebccSVladimir Oltean 		CLKSRC_IDIV3,
2568aa9ebccSVladimir Oltean 		CLKSRC_IDIV4,
2578aa9ebccSVladimir Oltean 	};
2588aa9ebccSVladimir Oltean 
259c5037678SVladimir Oltean 	if (regs->mii_ext_rx_clk[port] == SJA1105_RSV_ADDR)
260c5037678SVladimir Oltean 		return 0;
261c5037678SVladimir Oltean 
2628aa9ebccSVladimir Oltean 	/* Payload for packed_buf */
2638aa9ebccSVladimir Oltean 	mii_ext_rx_clk.clksrc    = clk_sources[port];
2648aa9ebccSVladimir Oltean 	mii_ext_rx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
2658aa9ebccSVladimir Oltean 	mii_ext_rx_clk.pd        = 0; /* Power Down off => enabled */
2668aa9ebccSVladimir Oltean 	sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_rx_clk, PACK);
2678aa9ebccSVladimir Oltean 
2681bd44870SVladimir Oltean 	return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_rx_clk[port],
2698aa9ebccSVladimir Oltean 				packed_buf, SJA1105_SIZE_CGU_CMD);
2708aa9ebccSVladimir Oltean }
2718aa9ebccSVladimir Oltean 
sja1105_mii_clocking_setup(struct sja1105_private * priv,int port,sja1105_mii_role_t role)2728aa9ebccSVladimir Oltean static int sja1105_mii_clocking_setup(struct sja1105_private *priv, int port,
2738aa9ebccSVladimir Oltean 				      sja1105_mii_role_t role)
2748aa9ebccSVladimir Oltean {
2758aa9ebccSVladimir Oltean 	struct device *dev = priv->ds->dev;
2768aa9ebccSVladimir Oltean 	int rc;
2778aa9ebccSVladimir Oltean 
2788aa9ebccSVladimir Oltean 	dev_dbg(dev, "Configuring MII-%s clocking\n",
2798aa9ebccSVladimir Oltean 		(role == XMII_MAC) ? "MAC" : "PHY");
2808aa9ebccSVladimir Oltean 	/* If role is MAC, disable IDIV
2818aa9ebccSVladimir Oltean 	 * If role is PHY, enable IDIV and configure for 1/1 divider
2828aa9ebccSVladimir Oltean 	 */
2838aa9ebccSVladimir Oltean 	rc = sja1105_cgu_idiv_config(priv, port, (role == XMII_PHY), 1);
2848aa9ebccSVladimir Oltean 	if (rc < 0)
2858aa9ebccSVladimir Oltean 		return rc;
2868aa9ebccSVladimir Oltean 
2878aa9ebccSVladimir Oltean 	/* Configure CLKSRC of MII_TX_CLK_n
2888aa9ebccSVladimir Oltean 	 *   * If role is MAC, select TX_CLK_n
2898aa9ebccSVladimir Oltean 	 *   * If role is PHY, select IDIV_n
2908aa9ebccSVladimir Oltean 	 */
2918aa9ebccSVladimir Oltean 	rc = sja1105_cgu_mii_tx_clk_config(priv, port, role);
2928aa9ebccSVladimir Oltean 	if (rc < 0)
2938aa9ebccSVladimir Oltean 		return rc;
2948aa9ebccSVladimir Oltean 
2958aa9ebccSVladimir Oltean 	/* Configure CLKSRC of MII_RX_CLK_n
2968aa9ebccSVladimir Oltean 	 * Select RX_CLK_n
2978aa9ebccSVladimir Oltean 	 */
2988aa9ebccSVladimir Oltean 	rc = sja1105_cgu_mii_rx_clk_config(priv, port);
2998aa9ebccSVladimir Oltean 	if (rc < 0)
3008aa9ebccSVladimir Oltean 		return rc;
3018aa9ebccSVladimir Oltean 
3028aa9ebccSVladimir Oltean 	if (role == XMII_PHY) {
3038aa9ebccSVladimir Oltean 		/* Per MII spec, the PHY (which is us) drives the TX_CLK pin */
3048aa9ebccSVladimir Oltean 
3058aa9ebccSVladimir Oltean 		/* Configure CLKSRC of EXT_TX_CLK_n
3068aa9ebccSVladimir Oltean 		 * Select IDIV_n
3078aa9ebccSVladimir Oltean 		 */
3088aa9ebccSVladimir Oltean 		rc = sja1105_cgu_mii_ext_tx_clk_config(priv, port);
3098aa9ebccSVladimir Oltean 		if (rc < 0)
3108aa9ebccSVladimir Oltean 			return rc;
3118aa9ebccSVladimir Oltean 
3128aa9ebccSVladimir Oltean 		/* Configure CLKSRC of EXT_RX_CLK_n
3138aa9ebccSVladimir Oltean 		 * Select IDIV_n
3148aa9ebccSVladimir Oltean 		 */
3158aa9ebccSVladimir Oltean 		rc = sja1105_cgu_mii_ext_rx_clk_config(priv, port);
3168aa9ebccSVladimir Oltean 		if (rc < 0)
3178aa9ebccSVladimir Oltean 			return rc;
3188aa9ebccSVladimir Oltean 	}
3198aa9ebccSVladimir Oltean 	return 0;
3208aa9ebccSVladimir Oltean }
3218aa9ebccSVladimir Oltean 
3228aa9ebccSVladimir Oltean static void
sja1105_cgu_pll_control_packing(void * buf,struct sja1105_cgu_pll_ctrl * cmd,enum packing_op op)3238aa9ebccSVladimir Oltean sja1105_cgu_pll_control_packing(void *buf, struct sja1105_cgu_pll_ctrl *cmd,
3248aa9ebccSVladimir Oltean 				enum packing_op op)
3258aa9ebccSVladimir Oltean {
3268aa9ebccSVladimir Oltean 	const int size = 4;
3278aa9ebccSVladimir Oltean 
3288aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->pllclksrc, 28, 24, size, op);
3298aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->msel,      23, 16, size, op);
3308aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op);
3318aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->psel,       9,  8, size, op);
3328aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->direct,     7,  7, size, op);
3338aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->fbsel,      6,  6, size, op);
3348aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->bypass,     1,  1, size, op);
3358aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->pd,         0,  0, size, op);
3368aa9ebccSVladimir Oltean }
3378aa9ebccSVladimir Oltean 
sja1105_cgu_rgmii_tx_clk_config(struct sja1105_private * priv,int port,u64 speed)3388aa9ebccSVladimir Oltean static int sja1105_cgu_rgmii_tx_clk_config(struct sja1105_private *priv,
33941fed17fSVladimir Oltean 					   int port, u64 speed)
3408aa9ebccSVladimir Oltean {
3418aa9ebccSVladimir Oltean 	const struct sja1105_regs *regs = priv->info->regs;
3428aa9ebccSVladimir Oltean 	struct sja1105_cgu_mii_ctrl txc;
3438aa9ebccSVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
3448aa9ebccSVladimir Oltean 	int clksrc;
3458aa9ebccSVladimir Oltean 
346c5037678SVladimir Oltean 	if (regs->rgmii_tx_clk[port] == SJA1105_RSV_ADDR)
347c5037678SVladimir Oltean 		return 0;
348c5037678SVladimir Oltean 
34941fed17fSVladimir Oltean 	if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS]) {
3508aa9ebccSVladimir Oltean 		clksrc = CLKSRC_PLL0;
3518aa9ebccSVladimir Oltean 	} else {
3528aa9ebccSVladimir Oltean 		int clk_sources[] = {CLKSRC_IDIV0, CLKSRC_IDIV1, CLKSRC_IDIV2,
3538aa9ebccSVladimir Oltean 				     CLKSRC_IDIV3, CLKSRC_IDIV4};
3548aa9ebccSVladimir Oltean 		clksrc = clk_sources[port];
3558aa9ebccSVladimir Oltean 	}
3568aa9ebccSVladimir Oltean 
3578aa9ebccSVladimir Oltean 	/* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */
3588aa9ebccSVladimir Oltean 	txc.clksrc = clksrc;
3598aa9ebccSVladimir Oltean 	/* Autoblock clk while changing clksrc */
3608aa9ebccSVladimir Oltean 	txc.autoblock = 1;
3618aa9ebccSVladimir Oltean 	/* Power Down off => enabled */
3628aa9ebccSVladimir Oltean 	txc.pd = 0;
3638aa9ebccSVladimir Oltean 	sja1105_cgu_mii_control_packing(packed_buf, &txc, PACK);
3648aa9ebccSVladimir Oltean 
3651bd44870SVladimir Oltean 	return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgmii_tx_clk[port],
3668aa9ebccSVladimir Oltean 				packed_buf, SJA1105_SIZE_CGU_CMD);
3678aa9ebccSVladimir Oltean }
3688aa9ebccSVladimir Oltean 
3698aa9ebccSVladimir Oltean /* AGU */
3708aa9ebccSVladimir Oltean static void
sja1105_cfg_pad_mii_packing(void * buf,struct sja1105_cfg_pad_mii * cmd,enum packing_op op)371135e3018SVladimir Oltean sja1105_cfg_pad_mii_packing(void *buf, struct sja1105_cfg_pad_mii *cmd,
3728aa9ebccSVladimir Oltean 			    enum packing_op op)
3738aa9ebccSVladimir Oltean {
3748aa9ebccSVladimir Oltean 	const int size = 4;
3758aa9ebccSVladimir Oltean 
3768aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->d32_os,   28, 27, size, op);
377135e3018SVladimir Oltean 	sja1105_packing(buf, &cmd->d32_ih,   26, 26, size, op);
3788aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->d32_ipud, 25, 24, size, op);
3798aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->d10_os,   20, 19, size, op);
380135e3018SVladimir Oltean 	sja1105_packing(buf, &cmd->d10_ih,   18, 18, size, op);
3818aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->d10_ipud, 17, 16, size, op);
3828aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->ctrl_os,  12, 11, size, op);
383135e3018SVladimir Oltean 	sja1105_packing(buf, &cmd->ctrl_ih,  10, 10, size, op);
3848aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->ctrl_ipud, 9,  8, size, op);
3858aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->clk_os,    4,  3, size, op);
3868aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->clk_ih,    2,  2, size, op);
3878aa9ebccSVladimir Oltean 	sja1105_packing(buf, &cmd->clk_ipud,  1,  0, size, op);
3888aa9ebccSVladimir Oltean }
3898aa9ebccSVladimir Oltean 
sja1105_rgmii_cfg_pad_tx_config(struct sja1105_private * priv,int port)3908aa9ebccSVladimir Oltean static int sja1105_rgmii_cfg_pad_tx_config(struct sja1105_private *priv,
3918aa9ebccSVladimir Oltean 					   int port)
3928aa9ebccSVladimir Oltean {
3938aa9ebccSVladimir Oltean 	const struct sja1105_regs *regs = priv->info->regs;
394135e3018SVladimir Oltean 	struct sja1105_cfg_pad_mii pad_mii_tx = {0};
3958aa9ebccSVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
3968aa9ebccSVladimir Oltean 
397c5037678SVladimir Oltean 	if (regs->pad_mii_tx[port] == SJA1105_RSV_ADDR)
398c5037678SVladimir Oltean 		return 0;
399c5037678SVladimir Oltean 
4008aa9ebccSVladimir Oltean 	/* Payload */
4018aa9ebccSVladimir Oltean 	pad_mii_tx.d32_os    = 3; /* TXD[3:2] output stage: */
4028aa9ebccSVladimir Oltean 				  /*          high noise/high speed */
4038aa9ebccSVladimir Oltean 	pad_mii_tx.d10_os    = 3; /* TXD[1:0] output stage: */
4048aa9ebccSVladimir Oltean 				  /*          high noise/high speed */
4058aa9ebccSVladimir Oltean 	pad_mii_tx.d32_ipud  = 2; /* TXD[3:2] input stage: */
4068aa9ebccSVladimir Oltean 				  /*          plain input (default) */
4078aa9ebccSVladimir Oltean 	pad_mii_tx.d10_ipud  = 2; /* TXD[1:0] input stage: */
4088aa9ebccSVladimir Oltean 				  /*          plain input (default) */
4098aa9ebccSVladimir Oltean 	pad_mii_tx.ctrl_os   = 3; /* TX_CTL / TX_ER output stage */
4108aa9ebccSVladimir Oltean 	pad_mii_tx.ctrl_ipud = 2; /* TX_CTL / TX_ER input stage (default) */
4118aa9ebccSVladimir Oltean 	pad_mii_tx.clk_os    = 3; /* TX_CLK output stage */
4128aa9ebccSVladimir Oltean 	pad_mii_tx.clk_ih    = 0; /* TX_CLK input hysteresis (default) */
4138aa9ebccSVladimir Oltean 	pad_mii_tx.clk_ipud  = 2; /* TX_CLK input stage (default) */
414135e3018SVladimir Oltean 	sja1105_cfg_pad_mii_packing(packed_buf, &pad_mii_tx, PACK);
4158aa9ebccSVladimir Oltean 
4161bd44870SVladimir Oltean 	return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_tx[port],
4178aa9ebccSVladimir Oltean 				packed_buf, SJA1105_SIZE_CGU_CMD);
4188aa9ebccSVladimir Oltean }
4198aa9ebccSVladimir Oltean 
sja1105_cfg_pad_rx_config(struct sja1105_private * priv,int port)420135e3018SVladimir Oltean static int sja1105_cfg_pad_rx_config(struct sja1105_private *priv, int port)
421135e3018SVladimir Oltean {
422135e3018SVladimir Oltean 	const struct sja1105_regs *regs = priv->info->regs;
423135e3018SVladimir Oltean 	struct sja1105_cfg_pad_mii pad_mii_rx = {0};
424135e3018SVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
425135e3018SVladimir Oltean 
426c5037678SVladimir Oltean 	if (regs->pad_mii_rx[port] == SJA1105_RSV_ADDR)
427c5037678SVladimir Oltean 		return 0;
428c5037678SVladimir Oltean 
429135e3018SVladimir Oltean 	/* Payload */
430135e3018SVladimir Oltean 	pad_mii_rx.d32_ih    = 0; /* RXD[3:2] input stage hysteresis: */
431135e3018SVladimir Oltean 				  /*          non-Schmitt (default) */
432135e3018SVladimir Oltean 	pad_mii_rx.d32_ipud  = 2; /* RXD[3:2] input weak pull-up/down */
433135e3018SVladimir Oltean 				  /*          plain input (default) */
434135e3018SVladimir Oltean 	pad_mii_rx.d10_ih    = 0; /* RXD[1:0] input stage hysteresis: */
435135e3018SVladimir Oltean 				  /*          non-Schmitt (default) */
436135e3018SVladimir Oltean 	pad_mii_rx.d10_ipud  = 2; /* RXD[1:0] input weak pull-up/down */
437135e3018SVladimir Oltean 				  /*          plain input (default) */
438135e3018SVladimir Oltean 	pad_mii_rx.ctrl_ih   = 0; /* RX_DV/CRS_DV/RX_CTL and RX_ER */
439135e3018SVladimir Oltean 				  /* input stage hysteresis: */
440135e3018SVladimir Oltean 				  /* non-Schmitt (default) */
441135e3018SVladimir Oltean 	pad_mii_rx.ctrl_ipud = 3; /* RX_DV/CRS_DV/RX_CTL and RX_ER */
442135e3018SVladimir Oltean 				  /* input stage weak pull-up/down: */
443135e3018SVladimir Oltean 				  /* pull-down */
444135e3018SVladimir Oltean 	pad_mii_rx.clk_os    = 2; /* RX_CLK/RXC output stage: */
445135e3018SVladimir Oltean 				  /* medium noise/fast speed (default) */
446135e3018SVladimir Oltean 	pad_mii_rx.clk_ih    = 0; /* RX_CLK/RXC input hysteresis: */
447135e3018SVladimir Oltean 				  /* non-Schmitt (default) */
448135e3018SVladimir Oltean 	pad_mii_rx.clk_ipud  = 2; /* RX_CLK/RXC input pull-up/down: */
449135e3018SVladimir Oltean 				  /* plain input (default) */
450135e3018SVladimir Oltean 	sja1105_cfg_pad_mii_packing(packed_buf, &pad_mii_rx, PACK);
451135e3018SVladimir Oltean 
452135e3018SVladimir Oltean 	return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_rx[port],
453135e3018SVladimir Oltean 				packed_buf, SJA1105_SIZE_CGU_CMD);
454135e3018SVladimir Oltean }
455135e3018SVladimir Oltean 
456c05ec3d4SVladimir Oltean static void
sja1105_cfg_pad_mii_id_packing(void * buf,struct sja1105_cfg_pad_mii_id * cmd,enum packing_op op)457c05ec3d4SVladimir Oltean sja1105_cfg_pad_mii_id_packing(void *buf, struct sja1105_cfg_pad_mii_id *cmd,
458c05ec3d4SVladimir Oltean 			       enum packing_op op)
459c05ec3d4SVladimir Oltean {
460c05ec3d4SVladimir Oltean 	const int size = SJA1105_SIZE_CGU_CMD;
461c05ec3d4SVladimir Oltean 
462c05ec3d4SVladimir Oltean 	sja1105_packing(buf, &cmd->rxc_stable_ovr, 15, 15, size, op);
463c05ec3d4SVladimir Oltean 	sja1105_packing(buf, &cmd->rxc_delay,      14, 10, size, op);
464c05ec3d4SVladimir Oltean 	sja1105_packing(buf, &cmd->rxc_bypass,      9,  9, size, op);
465c05ec3d4SVladimir Oltean 	sja1105_packing(buf, &cmd->rxc_pd,          8,  8, size, op);
466c05ec3d4SVladimir Oltean 	sja1105_packing(buf, &cmd->txc_stable_ovr,  7,  7, size, op);
467c05ec3d4SVladimir Oltean 	sja1105_packing(buf, &cmd->txc_delay,       6,  2, size, op);
468c05ec3d4SVladimir Oltean 	sja1105_packing(buf, &cmd->txc_bypass,      1,  1, size, op);
469c05ec3d4SVladimir Oltean 	sja1105_packing(buf, &cmd->txc_pd,          0,  0, size, op);
470c05ec3d4SVladimir Oltean }
471c05ec3d4SVladimir Oltean 
4723e77e59bSVladimir Oltean static void
sja1110_cfg_pad_mii_id_packing(void * buf,struct sja1105_cfg_pad_mii_id * cmd,enum packing_op op)4733e77e59bSVladimir Oltean sja1110_cfg_pad_mii_id_packing(void *buf, struct sja1105_cfg_pad_mii_id *cmd,
4743e77e59bSVladimir Oltean 			       enum packing_op op)
4753e77e59bSVladimir Oltean {
4763e77e59bSVladimir Oltean 	const int size = SJA1105_SIZE_CGU_CMD;
4773e77e59bSVladimir Oltean 	u64 range = 4;
4783e77e59bSVladimir Oltean 
4793e77e59bSVladimir Oltean 	/* Fields RXC_RANGE and TXC_RANGE select the input frequency range:
4803e77e59bSVladimir Oltean 	 * 0 = 2.5MHz
4813e77e59bSVladimir Oltean 	 * 1 = 25MHz
4823e77e59bSVladimir Oltean 	 * 2 = 50MHz
4833e77e59bSVladimir Oltean 	 * 3 = 125MHz
4843e77e59bSVladimir Oltean 	 * 4 = Automatically determined by port speed.
4853e77e59bSVladimir Oltean 	 * There's no point in defining a structure different than the one for
4863e77e59bSVladimir Oltean 	 * SJA1105, so just hardcode the frequency range to automatic, just as
4873e77e59bSVladimir Oltean 	 * before.
4883e77e59bSVladimir Oltean 	 */
4893e77e59bSVladimir Oltean 	sja1105_packing(buf, &cmd->rxc_stable_ovr, 26, 26, size, op);
4903e77e59bSVladimir Oltean 	sja1105_packing(buf, &cmd->rxc_delay,      25, 21, size, op);
4913e77e59bSVladimir Oltean 	sja1105_packing(buf, &range,               20, 18, size, op);
4923e77e59bSVladimir Oltean 	sja1105_packing(buf, &cmd->rxc_bypass,     17, 17, size, op);
4933e77e59bSVladimir Oltean 	sja1105_packing(buf, &cmd->rxc_pd,         16, 16, size, op);
4943e77e59bSVladimir Oltean 	sja1105_packing(buf, &cmd->txc_stable_ovr, 10, 10, size, op);
4953e77e59bSVladimir Oltean 	sja1105_packing(buf, &cmd->txc_delay,       9,  5, size, op);
4963e77e59bSVladimir Oltean 	sja1105_packing(buf, &range,                4,  2, size, op);
4973e77e59bSVladimir Oltean 	sja1105_packing(buf, &cmd->txc_bypass,      1,  1, size, op);
4983e77e59bSVladimir Oltean 	sja1105_packing(buf, &cmd->txc_pd,          0,  0, size, op);
4993e77e59bSVladimir Oltean }
5003e77e59bSVladimir Oltean 
501c05ec3d4SVladimir Oltean /* The RGMII delay setup procedure is 2-step and gets called upon each
502c05ec3d4SVladimir Oltean  * .phylink_mac_config. Both are strategic.
503c05ec3d4SVladimir Oltean  * The reason is that the RX Tunable Delay Line of the SJA1105 MAC has issues
504c05ec3d4SVladimir Oltean  * with recovering from a frequency change of the link partner's RGMII clock.
505c05ec3d4SVladimir Oltean  * The easiest way to recover from this is to temporarily power down the TDL,
506c05ec3d4SVladimir Oltean  * as it will re-lock at the new frequency afterwards.
507c05ec3d4SVladimir Oltean  */
sja1105pqrs_setup_rgmii_delay(const void * ctx,int port)508c05ec3d4SVladimir Oltean int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port)
509c05ec3d4SVladimir Oltean {
510c05ec3d4SVladimir Oltean 	const struct sja1105_private *priv = ctx;
511c05ec3d4SVladimir Oltean 	const struct sja1105_regs *regs = priv->info->regs;
512c05ec3d4SVladimir Oltean 	struct sja1105_cfg_pad_mii_id pad_mii_id = {0};
513*9ca482a2SVladimir Oltean 	int rx_delay = priv->rgmii_rx_delay_ps[port];
514*9ca482a2SVladimir Oltean 	int tx_delay = priv->rgmii_tx_delay_ps[port];
515c05ec3d4SVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
516c05ec3d4SVladimir Oltean 	int rc;
517c05ec3d4SVladimir Oltean 
518*9ca482a2SVladimir Oltean 	if (rx_delay)
519*9ca482a2SVladimir Oltean 		pad_mii_id.rxc_delay = SJA1105_RGMII_DELAY_PS_TO_HW(rx_delay);
520*9ca482a2SVladimir Oltean 	if (tx_delay)
521*9ca482a2SVladimir Oltean 		pad_mii_id.txc_delay = SJA1105_RGMII_DELAY_PS_TO_HW(tx_delay);
522c05ec3d4SVladimir Oltean 
523c05ec3d4SVladimir Oltean 	/* Stage 1: Turn the RGMII delay lines off. */
524c05ec3d4SVladimir Oltean 	pad_mii_id.rxc_bypass = 1;
525c05ec3d4SVladimir Oltean 	pad_mii_id.rxc_pd = 1;
526c05ec3d4SVladimir Oltean 	pad_mii_id.txc_bypass = 1;
527c05ec3d4SVladimir Oltean 	pad_mii_id.txc_pd = 1;
528c05ec3d4SVladimir Oltean 	sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);
529c05ec3d4SVladimir Oltean 
5301bd44870SVladimir Oltean 	rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
531c05ec3d4SVladimir Oltean 			      packed_buf, SJA1105_SIZE_CGU_CMD);
532c05ec3d4SVladimir Oltean 	if (rc < 0)
533c05ec3d4SVladimir Oltean 		return rc;
534c05ec3d4SVladimir Oltean 
535c05ec3d4SVladimir Oltean 	/* Stage 2: Turn the RGMII delay lines on. */
536*9ca482a2SVladimir Oltean 	if (rx_delay) {
537c05ec3d4SVladimir Oltean 		pad_mii_id.rxc_bypass = 0;
538c05ec3d4SVladimir Oltean 		pad_mii_id.rxc_pd = 0;
539c05ec3d4SVladimir Oltean 	}
540*9ca482a2SVladimir Oltean 	if (tx_delay) {
541c05ec3d4SVladimir Oltean 		pad_mii_id.txc_bypass = 0;
542c05ec3d4SVladimir Oltean 		pad_mii_id.txc_pd = 0;
543c05ec3d4SVladimir Oltean 	}
544c05ec3d4SVladimir Oltean 	sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);
545c05ec3d4SVladimir Oltean 
5461bd44870SVladimir Oltean 	return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
547c05ec3d4SVladimir Oltean 				packed_buf, SJA1105_SIZE_CGU_CMD);
548c05ec3d4SVladimir Oltean }
549c05ec3d4SVladimir Oltean 
sja1110_setup_rgmii_delay(const void * ctx,int port)5503e77e59bSVladimir Oltean int sja1110_setup_rgmii_delay(const void *ctx, int port)
5513e77e59bSVladimir Oltean {
5523e77e59bSVladimir Oltean 	const struct sja1105_private *priv = ctx;
5533e77e59bSVladimir Oltean 	const struct sja1105_regs *regs = priv->info->regs;
5543e77e59bSVladimir Oltean 	struct sja1105_cfg_pad_mii_id pad_mii_id = {0};
555*9ca482a2SVladimir Oltean 	int rx_delay = priv->rgmii_rx_delay_ps[port];
556*9ca482a2SVladimir Oltean 	int tx_delay = priv->rgmii_tx_delay_ps[port];
5573e77e59bSVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
5583e77e59bSVladimir Oltean 
5593e77e59bSVladimir Oltean 	pad_mii_id.rxc_pd = 1;
5603e77e59bSVladimir Oltean 	pad_mii_id.txc_pd = 1;
5613e77e59bSVladimir Oltean 
562*9ca482a2SVladimir Oltean 	if (rx_delay) {
563*9ca482a2SVladimir Oltean 		pad_mii_id.rxc_delay = SJA1105_RGMII_DELAY_PS_TO_HW(rx_delay);
5643e77e59bSVladimir Oltean 		/* The "BYPASS" bit in SJA1110 is actually a "don't bypass" */
5653e77e59bSVladimir Oltean 		pad_mii_id.rxc_bypass = 1;
5663e77e59bSVladimir Oltean 		pad_mii_id.rxc_pd = 0;
5673e77e59bSVladimir Oltean 	}
5683e77e59bSVladimir Oltean 
569*9ca482a2SVladimir Oltean 	if (tx_delay) {
570*9ca482a2SVladimir Oltean 		pad_mii_id.txc_delay = SJA1105_RGMII_DELAY_PS_TO_HW(tx_delay);
5713e77e59bSVladimir Oltean 		pad_mii_id.txc_bypass = 1;
5723e77e59bSVladimir Oltean 		pad_mii_id.txc_pd = 0;
5733e77e59bSVladimir Oltean 	}
5743e77e59bSVladimir Oltean 
5753e77e59bSVladimir Oltean 	sja1110_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);
5763e77e59bSVladimir Oltean 
5773e77e59bSVladimir Oltean 	return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
5783e77e59bSVladimir Oltean 				packed_buf, SJA1105_SIZE_CGU_CMD);
5793e77e59bSVladimir Oltean }
5803e77e59bSVladimir Oltean 
sja1105_rgmii_clocking_setup(struct sja1105_private * priv,int port,sja1105_mii_role_t role)581c05ec3d4SVladimir Oltean static int sja1105_rgmii_clocking_setup(struct sja1105_private *priv, int port,
582c05ec3d4SVladimir Oltean 					sja1105_mii_role_t role)
5838aa9ebccSVladimir Oltean {
5848aa9ebccSVladimir Oltean 	struct device *dev = priv->ds->dev;
5858aa9ebccSVladimir Oltean 	struct sja1105_mac_config_entry *mac;
58641fed17fSVladimir Oltean 	u64 speed;
5878aa9ebccSVladimir Oltean 	int rc;
5888aa9ebccSVladimir Oltean 
5898aa9ebccSVladimir Oltean 	mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
5908aa9ebccSVladimir Oltean 	speed = mac[port].speed;
5918aa9ebccSVladimir Oltean 
59241fed17fSVladimir Oltean 	dev_dbg(dev, "Configuring port %d RGMII at speed %lldMbps\n",
5938aa9ebccSVladimir Oltean 		port, speed);
5948aa9ebccSVladimir Oltean 
59541fed17fSVladimir Oltean 	if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS]) {
5968aa9ebccSVladimir Oltean 		/* 1000Mbps, IDIV disabled (125 MHz) */
5978aa9ebccSVladimir Oltean 		rc = sja1105_cgu_idiv_config(priv, port, false, 1);
59841fed17fSVladimir Oltean 	} else if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS]) {
5998aa9ebccSVladimir Oltean 		/* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */
6008aa9ebccSVladimir Oltean 		rc = sja1105_cgu_idiv_config(priv, port, true, 1);
60141fed17fSVladimir Oltean 	} else if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS]) {
6028aa9ebccSVladimir Oltean 		/* 10Mbps, IDIV enabled, divide by 10 (2.5 MHz) */
6038aa9ebccSVladimir Oltean 		rc = sja1105_cgu_idiv_config(priv, port, true, 10);
60441fed17fSVladimir Oltean 	} else if (speed == priv->info->port_speed[SJA1105_SPEED_AUTO]) {
6058aa9ebccSVladimir Oltean 		/* Skip CGU configuration if there is no speed available
6068aa9ebccSVladimir Oltean 		 * (e.g. link is not established yet)
6078aa9ebccSVladimir Oltean 		 */
6088aa9ebccSVladimir Oltean 		dev_dbg(dev, "Speed not available, skipping CGU config\n");
6098aa9ebccSVladimir Oltean 		return 0;
61041fed17fSVladimir Oltean 	} else {
6118aa9ebccSVladimir Oltean 		rc = -EINVAL;
6128aa9ebccSVladimir Oltean 	}
6138aa9ebccSVladimir Oltean 
6148aa9ebccSVladimir Oltean 	if (rc < 0) {
6158aa9ebccSVladimir Oltean 		dev_err(dev, "Failed to configure idiv\n");
6168aa9ebccSVladimir Oltean 		return rc;
6178aa9ebccSVladimir Oltean 	}
6188aa9ebccSVladimir Oltean 	rc = sja1105_cgu_rgmii_tx_clk_config(priv, port, speed);
6198aa9ebccSVladimir Oltean 	if (rc < 0) {
6208aa9ebccSVladimir Oltean 		dev_err(dev, "Failed to configure RGMII Tx clock\n");
6218aa9ebccSVladimir Oltean 		return rc;
6228aa9ebccSVladimir Oltean 	}
6238aa9ebccSVladimir Oltean 	rc = sja1105_rgmii_cfg_pad_tx_config(priv, port);
6248aa9ebccSVladimir Oltean 	if (rc < 0) {
6258aa9ebccSVladimir Oltean 		dev_err(dev, "Failed to configure Tx pad registers\n");
6268aa9ebccSVladimir Oltean 		return rc;
6278aa9ebccSVladimir Oltean 	}
628f41fad3cSVladimir Oltean 
629f5b8631cSVladimir Oltean 	if (!priv->info->setup_rgmii_delay)
6308aa9ebccSVladimir Oltean 		return 0;
631f5b8631cSVladimir Oltean 
632f5b8631cSVladimir Oltean 	return priv->info->setup_rgmii_delay(priv, port);
6338aa9ebccSVladimir Oltean }
6348aa9ebccSVladimir Oltean 
sja1105_cgu_rmii_ref_clk_config(struct sja1105_private * priv,int port)6358aa9ebccSVladimir Oltean static int sja1105_cgu_rmii_ref_clk_config(struct sja1105_private *priv,
6368aa9ebccSVladimir Oltean 					   int port)
6378aa9ebccSVladimir Oltean {
6388aa9ebccSVladimir Oltean 	const struct sja1105_regs *regs = priv->info->regs;
6398aa9ebccSVladimir Oltean 	struct sja1105_cgu_mii_ctrl ref_clk;
6408aa9ebccSVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
6418aa9ebccSVladimir Oltean 	const int clk_sources[] = {
6428aa9ebccSVladimir Oltean 		CLKSRC_MII0_TX_CLK,
6438aa9ebccSVladimir Oltean 		CLKSRC_MII1_TX_CLK,
6448aa9ebccSVladimir Oltean 		CLKSRC_MII2_TX_CLK,
6458aa9ebccSVladimir Oltean 		CLKSRC_MII3_TX_CLK,
6468aa9ebccSVladimir Oltean 		CLKSRC_MII4_TX_CLK,
6478aa9ebccSVladimir Oltean 	};
6488aa9ebccSVladimir Oltean 
649c5037678SVladimir Oltean 	if (regs->rmii_ref_clk[port] == SJA1105_RSV_ADDR)
650c5037678SVladimir Oltean 		return 0;
651c5037678SVladimir Oltean 
6528aa9ebccSVladimir Oltean 	/* Payload for packed_buf */
6538aa9ebccSVladimir Oltean 	ref_clk.clksrc    = clk_sources[port];
6548aa9ebccSVladimir Oltean 	ref_clk.autoblock = 1;      /* Autoblock clk while changing clksrc */
6558aa9ebccSVladimir Oltean 	ref_clk.pd        = 0;      /* Power Down off => enabled */
6568aa9ebccSVladimir Oltean 	sja1105_cgu_mii_control_packing(packed_buf, &ref_clk, PACK);
6578aa9ebccSVladimir Oltean 
6581bd44870SVladimir Oltean 	return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ref_clk[port],
6598aa9ebccSVladimir Oltean 				packed_buf, SJA1105_SIZE_CGU_CMD);
6608aa9ebccSVladimir Oltean }
6618aa9ebccSVladimir Oltean 
6628aa9ebccSVladimir Oltean static int
sja1105_cgu_rmii_ext_tx_clk_config(struct sja1105_private * priv,int port)6638aa9ebccSVladimir Oltean sja1105_cgu_rmii_ext_tx_clk_config(struct sja1105_private *priv, int port)
6648aa9ebccSVladimir Oltean {
6658aa9ebccSVladimir Oltean 	const struct sja1105_regs *regs = priv->info->regs;
6668aa9ebccSVladimir Oltean 	struct sja1105_cgu_mii_ctrl ext_tx_clk;
6678aa9ebccSVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
6688aa9ebccSVladimir Oltean 
669c5037678SVladimir Oltean 	if (regs->rmii_ext_tx_clk[port] == SJA1105_RSV_ADDR)
670c5037678SVladimir Oltean 		return 0;
671c5037678SVladimir Oltean 
6728aa9ebccSVladimir Oltean 	/* Payload for packed_buf */
6738aa9ebccSVladimir Oltean 	ext_tx_clk.clksrc    = CLKSRC_PLL1;
6748aa9ebccSVladimir Oltean 	ext_tx_clk.autoblock = 1;   /* Autoblock clk while changing clksrc */
6758aa9ebccSVladimir Oltean 	ext_tx_clk.pd        = 0;   /* Power Down off => enabled */
6768aa9ebccSVladimir Oltean 	sja1105_cgu_mii_control_packing(packed_buf, &ext_tx_clk, PACK);
6778aa9ebccSVladimir Oltean 
6781bd44870SVladimir Oltean 	return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ext_tx_clk[port],
6798aa9ebccSVladimir Oltean 				packed_buf, SJA1105_SIZE_CGU_CMD);
6808aa9ebccSVladimir Oltean }
6818aa9ebccSVladimir Oltean 
sja1105_cgu_rmii_pll_config(struct sja1105_private * priv)6828aa9ebccSVladimir Oltean static int sja1105_cgu_rmii_pll_config(struct sja1105_private *priv)
6838aa9ebccSVladimir Oltean {
6848aa9ebccSVladimir Oltean 	const struct sja1105_regs *regs = priv->info->regs;
6858aa9ebccSVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
6868aa9ebccSVladimir Oltean 	struct sja1105_cgu_pll_ctrl pll = {0};
6878aa9ebccSVladimir Oltean 	struct device *dev = priv->ds->dev;
6888aa9ebccSVladimir Oltean 	int rc;
6898aa9ebccSVladimir Oltean 
690c5037678SVladimir Oltean 	if (regs->rmii_pll1 == SJA1105_RSV_ADDR)
691c5037678SVladimir Oltean 		return 0;
692c5037678SVladimir Oltean 
6938aa9ebccSVladimir Oltean 	/* PLL1 must be enabled and output 50 Mhz.
6948aa9ebccSVladimir Oltean 	 * This is done by writing first 0x0A010941 to
6958aa9ebccSVladimir Oltean 	 * the PLL_1_C register and then deasserting
6968aa9ebccSVladimir Oltean 	 * power down (PD) 0x0A010940.
6978aa9ebccSVladimir Oltean 	 */
6988aa9ebccSVladimir Oltean 
6998aa9ebccSVladimir Oltean 	/* Step 1: PLL1 setup for 50Mhz */
7008aa9ebccSVladimir Oltean 	pll.pllclksrc = 0xA;
7018aa9ebccSVladimir Oltean 	pll.msel      = 0x1;
7028aa9ebccSVladimir Oltean 	pll.autoblock = 0x1;
7038aa9ebccSVladimir Oltean 	pll.psel      = 0x1;
7048aa9ebccSVladimir Oltean 	pll.direct    = 0x0;
7058aa9ebccSVladimir Oltean 	pll.fbsel     = 0x1;
7068aa9ebccSVladimir Oltean 	pll.bypass    = 0x0;
7078aa9ebccSVladimir Oltean 	pll.pd        = 0x1;
7088aa9ebccSVladimir Oltean 
7098aa9ebccSVladimir Oltean 	sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
7101bd44870SVladimir Oltean 	rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf,
7111bd44870SVladimir Oltean 			      SJA1105_SIZE_CGU_CMD);
7128aa9ebccSVladimir Oltean 	if (rc < 0) {
7138aa9ebccSVladimir Oltean 		dev_err(dev, "failed to configure PLL1 for 50MHz\n");
7148aa9ebccSVladimir Oltean 		return rc;
7158aa9ebccSVladimir Oltean 	}
7168aa9ebccSVladimir Oltean 
7178aa9ebccSVladimir Oltean 	/* Step 2: Enable PLL1 */
7188aa9ebccSVladimir Oltean 	pll.pd = 0x0;
7198aa9ebccSVladimir Oltean 
7208aa9ebccSVladimir Oltean 	sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
7211bd44870SVladimir Oltean 	rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf,
7221bd44870SVladimir Oltean 			      SJA1105_SIZE_CGU_CMD);
7238aa9ebccSVladimir Oltean 	if (rc < 0) {
7248aa9ebccSVladimir Oltean 		dev_err(dev, "failed to enable PLL1\n");
7258aa9ebccSVladimir Oltean 		return rc;
7268aa9ebccSVladimir Oltean 	}
7278aa9ebccSVladimir Oltean 	return rc;
7288aa9ebccSVladimir Oltean }
7298aa9ebccSVladimir Oltean 
sja1105_rmii_clocking_setup(struct sja1105_private * priv,int port,sja1105_mii_role_t role)7308aa9ebccSVladimir Oltean static int sja1105_rmii_clocking_setup(struct sja1105_private *priv, int port,
7318aa9ebccSVladimir Oltean 				       sja1105_mii_role_t role)
7328aa9ebccSVladimir Oltean {
7338aa9ebccSVladimir Oltean 	struct device *dev = priv->ds->dev;
7348aa9ebccSVladimir Oltean 	int rc;
7358aa9ebccSVladimir Oltean 
7368aa9ebccSVladimir Oltean 	dev_dbg(dev, "Configuring RMII-%s clocking\n",
7378aa9ebccSVladimir Oltean 		(role == XMII_MAC) ? "MAC" : "PHY");
7388aa9ebccSVladimir Oltean 	/* AH1601.pdf chapter 2.5.1. Sources */
7398aa9ebccSVladimir Oltean 	if (role == XMII_MAC) {
7408aa9ebccSVladimir Oltean 		/* Configure and enable PLL1 for 50Mhz output */
7418aa9ebccSVladimir Oltean 		rc = sja1105_cgu_rmii_pll_config(priv);
7428aa9ebccSVladimir Oltean 		if (rc < 0)
7438aa9ebccSVladimir Oltean 			return rc;
7448aa9ebccSVladimir Oltean 	}
7458aa9ebccSVladimir Oltean 	/* Disable IDIV for this port */
7468aa9ebccSVladimir Oltean 	rc = sja1105_cgu_idiv_config(priv, port, false, 1);
7478aa9ebccSVladimir Oltean 	if (rc < 0)
7488aa9ebccSVladimir Oltean 		return rc;
7498aa9ebccSVladimir Oltean 	/* Source to sink mappings */
7508aa9ebccSVladimir Oltean 	rc = sja1105_cgu_rmii_ref_clk_config(priv, port);
7518aa9ebccSVladimir Oltean 	if (rc < 0)
7528aa9ebccSVladimir Oltean 		return rc;
7538aa9ebccSVladimir Oltean 	if (role == XMII_MAC) {
7548aa9ebccSVladimir Oltean 		rc = sja1105_cgu_rmii_ext_tx_clk_config(priv, port);
7558aa9ebccSVladimir Oltean 		if (rc < 0)
7568aa9ebccSVladimir Oltean 			return rc;
7578aa9ebccSVladimir Oltean 	}
7588aa9ebccSVladimir Oltean 	return 0;
7598aa9ebccSVladimir Oltean }
7608aa9ebccSVladimir Oltean 
sja1105_clocking_setup_port(struct sja1105_private * priv,int port)7618aa9ebccSVladimir Oltean int sja1105_clocking_setup_port(struct sja1105_private *priv, int port)
7628aa9ebccSVladimir Oltean {
7638aa9ebccSVladimir Oltean 	struct sja1105_xmii_params_entry *mii;
7648aa9ebccSVladimir Oltean 	struct device *dev = priv->ds->dev;
7658aa9ebccSVladimir Oltean 	sja1105_phy_interface_t phy_mode;
7668aa9ebccSVladimir Oltean 	sja1105_mii_role_t role;
7678aa9ebccSVladimir Oltean 	int rc;
7688aa9ebccSVladimir Oltean 
7698aa9ebccSVladimir Oltean 	mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
7708aa9ebccSVladimir Oltean 
7718aa9ebccSVladimir Oltean 	/* RGMII etc */
7728aa9ebccSVladimir Oltean 	phy_mode = mii->xmii_mode[port];
7738aa9ebccSVladimir Oltean 	/* MAC or PHY, for applicable types (not RGMII) */
7748aa9ebccSVladimir Oltean 	role = mii->phy_mac[port];
7758aa9ebccSVladimir Oltean 
7768aa9ebccSVladimir Oltean 	switch (phy_mode) {
7778aa9ebccSVladimir Oltean 	case XMII_MODE_MII:
7788aa9ebccSVladimir Oltean 		rc = sja1105_mii_clocking_setup(priv, port, role);
7798aa9ebccSVladimir Oltean 		break;
7808aa9ebccSVladimir Oltean 	case XMII_MODE_RMII:
7818aa9ebccSVladimir Oltean 		rc = sja1105_rmii_clocking_setup(priv, port, role);
7828aa9ebccSVladimir Oltean 		break;
7838aa9ebccSVladimir Oltean 	case XMII_MODE_RGMII:
784c05ec3d4SVladimir Oltean 		rc = sja1105_rgmii_clocking_setup(priv, port, role);
7858aa9ebccSVladimir Oltean 		break;
786ffe10e67SVladimir Oltean 	case XMII_MODE_SGMII:
787ffe10e67SVladimir Oltean 		/* Nothing to do in the CGU for SGMII */
788ffe10e67SVladimir Oltean 		rc = 0;
789ffe10e67SVladimir Oltean 		break;
7908aa9ebccSVladimir Oltean 	default:
7918aa9ebccSVladimir Oltean 		dev_err(dev, "Invalid interface mode specified: %d\n",
7928aa9ebccSVladimir Oltean 			phy_mode);
7938aa9ebccSVladimir Oltean 		return -EINVAL;
7948aa9ebccSVladimir Oltean 	}
795135e3018SVladimir Oltean 	if (rc) {
7968aa9ebccSVladimir Oltean 		dev_err(dev, "Clocking setup for port %d failed: %d\n",
7978aa9ebccSVladimir Oltean 			port, rc);
7988aa9ebccSVladimir Oltean 		return rc;
7998aa9ebccSVladimir Oltean 	}
8008aa9ebccSVladimir Oltean 
801135e3018SVladimir Oltean 	/* Internally pull down the RX_DV/CRS_DV/RX_CTL and RX_ER inputs */
802135e3018SVladimir Oltean 	return sja1105_cfg_pad_rx_config(priv, port);
803135e3018SVladimir Oltean }
804135e3018SVladimir Oltean 
sja1105_clocking_setup(struct sja1105_private * priv)8058aa9ebccSVladimir Oltean int sja1105_clocking_setup(struct sja1105_private *priv)
8068aa9ebccSVladimir Oltean {
807542043e9SVladimir Oltean 	struct dsa_switch *ds = priv->ds;
8088aa9ebccSVladimir Oltean 	int port, rc;
8098aa9ebccSVladimir Oltean 
810542043e9SVladimir Oltean 	for (port = 0; port < ds->num_ports; port++) {
8118aa9ebccSVladimir Oltean 		rc = sja1105_clocking_setup_port(priv, port);
8128aa9ebccSVladimir Oltean 		if (rc < 0)
8138aa9ebccSVladimir Oltean 			return rc;
8148aa9ebccSVladimir Oltean 	}
8158aa9ebccSVladimir Oltean 	return 0;
8168aa9ebccSVladimir Oltean }
8173e77e59bSVladimir Oltean 
8183e77e59bSVladimir Oltean static void
sja1110_cgu_outclk_packing(void * buf,struct sja1110_cgu_outclk * outclk,enum packing_op op)8193e77e59bSVladimir Oltean sja1110_cgu_outclk_packing(void *buf, struct sja1110_cgu_outclk *outclk,
8203e77e59bSVladimir Oltean 			   enum packing_op op)
8213e77e59bSVladimir Oltean {
8223e77e59bSVladimir Oltean 	const int size = 4;
8233e77e59bSVladimir Oltean 
8243e77e59bSVladimir Oltean 	sja1105_packing(buf, &outclk->clksrc,    27, 24, size, op);
8253e77e59bSVladimir Oltean 	sja1105_packing(buf, &outclk->autoblock, 11, 11, size, op);
8263e77e59bSVladimir Oltean 	sja1105_packing(buf, &outclk->pd,         0,  0, size, op);
8273e77e59bSVladimir Oltean }
8283e77e59bSVladimir Oltean 
sja1110_disable_microcontroller(struct sja1105_private * priv)829cb5a82d2SVladimir Oltean int sja1110_disable_microcontroller(struct sja1105_private *priv)
8303e77e59bSVladimir Oltean {
8313e77e59bSVladimir Oltean 	u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
832cb5a82d2SVladimir Oltean 	struct sja1110_cgu_outclk outclk_6_c = {
833cb5a82d2SVladimir Oltean 		.clksrc = 0x3,
834cb5a82d2SVladimir Oltean 		.pd = true,
835cb5a82d2SVladimir Oltean 	};
8363e77e59bSVladimir Oltean 	struct sja1110_cgu_outclk outclk_7_c = {
8373e77e59bSVladimir Oltean 		.clksrc = 0x5,
8383e77e59bSVladimir Oltean 		.pd = true,
8393e77e59bSVladimir Oltean 	};
840cb5a82d2SVladimir Oltean 	int rc;
8413e77e59bSVladimir Oltean 
842cb5a82d2SVladimir Oltean 	/* Power down the BASE_TIMER_CLK to disable the watchdog timer */
8433e77e59bSVladimir Oltean 	sja1110_cgu_outclk_packing(packed_buf, &outclk_7_c, PACK);
8443e77e59bSVladimir Oltean 
845cb5a82d2SVladimir Oltean 	rc = sja1105_xfer_buf(priv, SPI_WRITE, SJA1110_BASE_TIMER_CLK,
846cb5a82d2SVladimir Oltean 			      packed_buf, SJA1105_SIZE_CGU_CMD);
847cb5a82d2SVladimir Oltean 	if (rc)
848cb5a82d2SVladimir Oltean 		return rc;
849cb5a82d2SVladimir Oltean 
850cb5a82d2SVladimir Oltean 	/* Power down the BASE_MCSS_CLOCK to gate the microcontroller off */
851cb5a82d2SVladimir Oltean 	sja1110_cgu_outclk_packing(packed_buf, &outclk_6_c, PACK);
852cb5a82d2SVladimir Oltean 
853cb5a82d2SVladimir Oltean 	return sja1105_xfer_buf(priv, SPI_WRITE, SJA1110_BASE_MCSS_CLK,
8543e77e59bSVladimir Oltean 				packed_buf, SJA1105_SIZE_CGU_CMD);
8553e77e59bSVladimir Oltean }
856