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/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dbaikal,bt1-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
21 const: baikal,bt1-ahci
[all …]
H A Dsnps,dwc-ahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
19 - $ref: ahci-common.yaml#
31 PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
36 clock-names:
41 - description: Application APB/AHB/AXI BIU clock
43 - pclk
[all …]
H A Dsnps,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
26 - $ref: snps,dwc-ahci-common.yaml#
31 - description: Synopsys AHCI SATA-compatible devices
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H A Drockchip,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
25 - compatible
30 - enum:
31 - rockchip,rk3568-dwc-ahci
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/openbmc/linux/drivers/net/wireless/ath/ath5k/
H A Ddesc.c2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
34 * Here we handle the processing of the low-level hw descriptors
35 * that hw reads and writes via DMA for each TX and RX attempt (that means
36 * we can also have descriptors for failed TX/RX tries). We have two kind of
37 * descriptors for RX and TX, control descriptors tell the hw how to send or
49 * TX Control descriptors *
53 * ath5k_hw_setup_2word_tx_desc() - Initialize a 2-word tx control descriptor
60 * @tx_power: Tx power in 0.5dB steps
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear1310-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear1310-evb", "st,spear1310";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
63 smi-pmx {
127 label = "u-boot";
149 compatible = "gpio-keys";
[all …]
H A Dspear1340-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear1340-evb", "st,spear1340";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
47 spdif-in {
51 spdif-out {
59 smi-pmx {
[all …]
/openbmc/linux/drivers/input/touchscreen/
H A Dads7846.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * - corgi_ts.c
11 * Copyright (C) 2004-2005 Richard Purdie
12 * - omap_ts.[hc], ads7846.h, ts_osk.c
39 * Support for ads7843 tested on Atmel at91sam926x-EK.
53 * note. The strength of filtering can be set in the board-* specific
76 * driver is used with DMA-based SPI controllers (like atmel_spi) on
77 * systems where main memory is not DMA-coherent (most non-x86 boards).
86 struct ads7846_buf *tx; member
151 /* leave chip selected when we're done, for quicker re-select? */
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/openbmc/linux/drivers/media/cec/core/
H A Dcec-pin.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <media/cec-pin.h>
11 #include "cec-pin-priv.h"
61 /* Data bits are 0-7, EOM is bit 8 and ACK is bit 9 */
73 { "Tx Wait", CEC_TIM_SAMPLE },
74 { "Tx Wait for High", CEC_TIM_IDLE_SAMPLE },
75 { "Tx Start Bit Low", CEC_TIM_START_BIT_LOW },
76 { "Tx Start Bit High", CEC_TIM_START_BIT_TOTAL - CEC_TIM_START_BIT_LOW },
77 { "Tx Start Bit High Short", CEC_TIM_START_BIT_TOTAL_SHORT - CEC_TIM_START_BIT_LOW },
78 { "Tx Start Bit High Long", CEC_TIM_START_BIT_TOTAL_LONG - CEC_TIM_START_BIT_LOW },
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc7280-crd-r3.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include "sc7280-idp.dtsi"
11 #include "sc7280-idp-ec-h1.dtsi"
14 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)";
15 compatible = "qcom,sc7280-crd",
16 "google,hoglin-rev3", "google,hoglin-rev4",
17 "google,piglin-rev3", "google,piglin-rev4",
25 stdout-path = "serial0:115200n8";
30 regulators-2 {
[all …]
H A Dsc7280-qcard.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
15 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
16 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
17 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
34 wcd9385: audio-codec-1 {
35 compatible = "qcom,wcd9385-codec";
36 pinctrl-names = "default", "sleep";
37 pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
38 pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>;
[all …]
H A Dmsm8998-fxtec-pro1.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
20 chassis-type = "handset";
21 qcom,board-id = <0x02000b 0x10>;
29 * Until we hook up type-c detection, we
32 extcon_usb: extcon-usb {
33 compatible = "linux,extcon-usb-gpio";
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dxmit.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
17 #include <linux/dma-mapping.h>
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
49 { 104, 216 }, /* 3: 16-QAM 1/2 */
50 { 156, 324 }, /* 4: 16-QAM 3/4 */
51 { 208, 432 }, /* 5: 64-QAM 2/3 */
52 { 234, 486 }, /* 6: 64-QAM 3/4 */
53 { 260, 540 }, /* 7: 64-QAM 5/6 */
64 struct ath_tx_status *ts, int txok);
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H A Ddynack.c27 * ath_dynack_get_max_to - set max timeout according to channel width
33 const struct ath9k_channel *chan = ah->curchan; in ath_dynack_get_max_to()
48 * ath_dynack_ewma - EWMA (Exponentially Weighted Moving Average) calculation
53 return (new * (EWMA_DIV - EWMA_LEVEL) + in ath_dynack_ewma()
60 * ath_dynack_get_sifs - get sifs time based on phy used
70 if (IS_CHAN_QUARTER_RATE(ah->curchan)) in ath_dynack_get_sifs()
72 else if (IS_CHAN_HALF_RATE(ah->curchan)) in ath_dynack_get_sifs()
81 * ath_dynack_bssidmask - filter out ACK frames based on BSSID mask
91 if ((common->macaddr[i] & common->bssidmask[i]) != in ath_dynack_bssidmask()
92 (mac[i] & common->bssidmask[i])) in ath_dynack_bssidmask()
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/openbmc/linux/drivers/net/wireless/quantenna/qtnfmac/pcie/
H A Dtopaz_pcie.c1 // SPDX-License-Identifier: GPL-2.0+
103 static void qtnf_deassert_intx(struct qtnf_pcie_topaz_state *ts) in qtnf_deassert_intx() argument
105 void __iomem *reg = ts->base.sysctl_bar + TOPAZ_PCIE_CFG0_OFFSET; in qtnf_deassert_intx()
113 static inline int qtnf_topaz_intx_asserted(struct qtnf_pcie_topaz_state *ts) in qtnf_topaz_intx_asserted() argument
115 void __iomem *reg = ts->base.sysctl_bar + TOPAZ_PCIE_CFG0_OFFSET; in qtnf_topaz_intx_asserted()
121 static void qtnf_topaz_reset_ep(struct qtnf_pcie_topaz_state *ts) in qtnf_topaz_reset_ep() argument
124 TOPAZ_LH_IPC4_INT(ts->base.sysctl_bar)); in qtnf_topaz_reset_ep()
126 pci_restore_state(ts->base.pdev); in qtnf_topaz_reset_ep()
129 static void setup_rx_irqs(struct qtnf_pcie_topaz_state *ts) in setup_rx_irqs() argument
131 void __iomem *reg = PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(ts->base.dmareg_bar); in setup_rx_irqs()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dzynq_spi.c1 // SPDX-License-Identifier: GPL-2.0+
30 #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
74 struct zynq_spi_platdata *plat = bus->platdata; in zynq_spi_ofdata_to_platdata()
75 const void *blob = gd->fdt_blob; in zynq_spi_ofdata_to_platdata()
78 plat->regs = (struct zynq_spi_regs *)devfdt_get_addr(bus); in zynq_spi_ofdata_to_platdata()
81 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", in zynq_spi_ofdata_to_platdata()
83 plat->deactivate_delay_us = fdtdec_get_int(blob, node, in zynq_spi_ofdata_to_platdata()
84 "spi-deactivate-delay", 0); in zynq_spi_ofdata_to_platdata()
85 plat->activate_delay_us = fdtdec_get_int(blob, node, in zynq_spi_ofdata_to_platdata()
86 "spi-activate-delay", 0); in zynq_spi_ofdata_to_platdata()
[all …]
/openbmc/u-boot/drivers/net/
H A Dftmac110.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Dante Su <dantesu@faraday-tech.com>
15 #include <asm/dma-mapping.h>
35 * accepts only 16-bits aligned address, 32-bits aligned is not
36 * acceptable. However this restriction does not apply to Tx DMA.
39 * (1) Tx DMA Buffer Address:
42 * 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
70 struct ftmac110_chip *chip = dev->priv; in mdio_read()
71 struct ftmac110_regs *regs = chip->regs; in mdio_read()
72 uint32_t tmp, ts; in mdio_read() local
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/openbmc/linux/drivers/ata/
H A Dahci_dwc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 #define DRV_NAME "ahci-dwc"
95 /* Baikal-T1 AHCI SATA specific registers */
127 struct ahci_dwc_host_priv *dpriv = hpriv->plat_data; in ahci_bt1_init()
134 dev_err(&dpriv->pdev->dev, "No system clocks specified\n"); in ahci_bt1_init()
135 return -EINVAL; in ahci_bt1_init()
145 dev_err(&dpriv->pdev->dev, "Couldn't assert the resets\n"); in ahci_bt1_init()
151 dev_err(&dpriv->pdev->dev, "Couldn't de-assert the resets\n"); in ahci_bt1_init()
163 dpriv = devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL); in ahci_dwc_get_resources()
165 return ERR_PTR(-ENOMEM); in ahci_dwc_get_resources()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
47 * +--------------+ +--------------+
49 * *--------------+ +--------------+
52 * +--------------+ +--------------+
54 * *--------------+ +--------------+
58 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
61 * 2^43 * 10^-9 / 3600 = 2.4 hours
89 * represents units of 2^-32 nanoseconds, and uses 31 bits for this, with the
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "rk3588-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
16 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
21 compatible = "rockchip,rk3588-i2s-tdm";
25 clock-names = "mclk_tx", "mclk_rx", "hclk";
26 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
27 assigned-clock-parents = <&cru PLL_AUPLL>;
29 dma-names = "tx";
30 power-domains = <&power RK3588_PD_VO0>;
[all …]
/openbmc/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-tef.c1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 // Marc Kleine-Budde <kernel@pengutronix.de>
36 err = regmap_read(priv->map_reg, MCP251XFD_REG_TEFUA, &tef_ua); in mcp251xfd_tef_tail_get_from_chip()
59 netdev_err(priv->ndev, in mcp251xfd_check_tef_tail()
62 return -EILSEQ; in mcp251xfd_check_tef_tail()
73 struct net_device_stats *stats = &priv->ndev->stats; in mcp251xfd_handle_tefif_one()
81 hw_tef_obj->flags); in mcp251xfd_handle_tefif_one()
82 tef_tail_masked = priv->tef->tail & in mcp251xfd_handle_tefif_one()
86 * bits of a FIFOSTA register, here the TX FIFO tail index in mcp251xfd_handle_tefif_one()
[all …]
/openbmc/linux/drivers/soc/fsl/qe/
H A Dqmc.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
52 /* Tx time-slot assignment table pointer (16 bits) */
64 /* Rx time-slot assignment table pointer (16 bits) */
66 /* Tx pointer (16 bits) */
72 /* Time slot assignment table Tx (32 x 16 bits) */
83 /* Tx buffer descriptor base address (16 bits, offset from MCBASE) */
98 /* Tx internal state (32 bits) */
100 /* Tx buffer descriptor pointer (16 bits) */
102 /* Zero-insertion state (32 bits) */
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
12 compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
15 stdout-path = &lpuart5;
23 reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
29 compatible = "shared-dma-pool";
32 linux,cma-default;
35 m33_reserved: noncacheable-section@a8600000 {
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x5ek.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
11 model = "Atmel AT91SAM9X5-EK";
16 stdout-path = "serial0:115200n8";
20 compatible = "atmel,sam9x5-wm8731-audio";
24 atmel,audio-routing =
30 atmel,ssc-controller = <&ssc0>;
31 atmel,audio-codec = <&wm8731>;
36 atmel,adc-ts-wires = <4>;
37 atmel,adc-ts-pressure-threshold = <10000>;
[all …]
/openbmc/u-boot/drivers/mmc/
H A Dftsdc010_mci.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Dante Su <dantesu@faraday-tech.com>
23 #include <dt-structs.h>
65 struct ftsdc010_chip *chip = mmc->priv; in ftsdc010_send_cmd()
66 struct ftsdc010_mmc __iomem *regs = chip->regs; in ftsdc010_send_cmd()
67 int ret = -ETIMEDOUT; in ftsdc010_send_cmd()
68 uint32_t ts, st; in ftsdc010_send_cmd() local
69 uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx); in ftsdc010_send_cmd()
70 uint32_t arg = mmc_cmd->cmdarg; in ftsdc010_send_cmd()
71 uint32_t flags = mmc_cmd->resp_type; in ftsdc010_send_cmd()
[all …]

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