| /openbmc/linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | atmel,sama5d2-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/atmel,sama5d2-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugen Hristev <eugen.hristev@microchip.com>
15 - atmel,sama5d2-adc
16 - microchip,sam9x60-adc
17 - microchip,sama7g5-adc
28 clock-names:
31 vref-supply: true
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| /openbmc/linux/drivers/gpio/ |
| H A D | gpio-tqmx86.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * TQ-Systems TQMx86 PLD GPIO driver
23 #define TQMX86_NGPO 4 /* 0-3 - output */
24 #define TQMX86_NGPI 4 /* 4-7 - input */
25 #define TQMX86_DIR_INPUT_MASK 0xf0 /* 0-3 - output, 4-7 - input */
35 /* Stored in irq_type as a trigger type, but not actually valid as a register
56 return ioread8(gd->io_base + reg); in tqmx86_gpio_read()
62 iowrite8(val, gd->io_base + reg); in tqmx86_gpio_write()
78 raw_spin_lock_irqsave(&gpio->spinlock, flags); in tqmx86_gpio_set()
79 __assign_bit(offset, gpio->output, value); in tqmx86_gpio_set()
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| H A D | gpio-mxc.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
34 /* device type dependent stuff */
86 .edge_sel_reg = -EINVAL,
101 .edge_sel_reg = -EINVAL,
123 #define GPIO_DR (port->hwdata->dr_reg)
124 #define GPIO_GDIR (port->hwdata->gdir_reg)
125 #define GPIO_PSR (port->hwdata->psr_reg)
126 #define GPIO_ICR1 (port->hwdata->icr1_reg)
127 #define GPIO_ICR2 (port->hwdata->icr2_reg)
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| H A D | gpio-omap.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2003-2005 Nokia Corporation
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
27 #include <linux/platform_data/gpio-omap.h>
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
121 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
125 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
126 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
128 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | ti,sci-intr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
18 to be driven per N output. An Interrupt Router can either handle edge
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
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| H A D | img,pdc-intc.txt | 10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
20 interrupt source. The type shall be a <u32> and the value shall be 2.
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
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| H A D | snps,archs-idu-intc.txt | 1 * ARC-HS Interrupt Distribution Unit
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
30 core_intc: core-interrupt-controller {
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| H A D | atmel,aic.txt | 4 - compatible: Should be:
5 - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
7 - "microchip,<chip>-aic" where <chip> can be "sam9x60"
9 - interrupt-controller: Identifies the node as an interrupt controller.
10 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
13 bits[3:0] trigger type and level flags:
14 1 = low-to-high edge triggered.
15 2 = high-to-low edge triggered.
16 4 = active high level-sensitive.
17 8 = active low level-sensitive.
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| H A D | socionext,uniphier-aidet.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/socionext,uniphier-aidet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC
12 rising edge interrupts. The AIDET provides logic inverter to support low
13 level and falling edge interrupts.
16 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 - $ref: /schemas/interrupt-controller.yaml#
24 - socionext,uniphier-ld4-aidet
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| H A D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
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| /openbmc/qemu/hw/intc/ |
| H A D | aspeed_vic.c | 9 * the COPYING file in the top-level directory.
24 * Additionally, the "Interrupt Enable", "Edge Status" and "Software Interrupt"
27 * read-modify-write sequence).
47 uint64_t new = (s->raw & s->enable); in aspeed_vic_update()
50 flags = new & s->select; in aspeed_vic_update()
52 qemu_set_irq(s->fiq, !!flags); in aspeed_vic_update()
54 flags = new & ~s->select; in aspeed_vic_update()
56 qemu_set_irq(s->irq, !!flags); in aspeed_vic_update()
74 if (s->sense & irq_mask) { in aspeed_vic_set_irq()
75 /* level-triggered */ in aspeed_vic_set_irq()
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| /openbmc/linux/Documentation/devicetree/bindings/mips/cavium/ |
| H A D | ciu3.txt | 4 - compatible: "cavium,octeon-7890-ciu3"
8 - interrupt-controller: This is an interrupt controller.
10 - reg: The base address of the CIU's register bank.
12 - #interrupt-cells: Must be <2>. The first cell is source number.
14 value of either 4 for level semantics, or 1 for edge semantics.
17 interrupt-controller@1010000000000 {
18 compatible = "cavium,octeon-7890-ciu3";
19 interrupt-controller;
22 * 2) Trigger type: (4 == level, 1 == edge)
24 #address-cells = <0>;
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| /openbmc/linux/drivers/comedi/drivers/ |
| H A D | addi_apci_1500.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
6 * ADDI-DATA GmbH
8 * D-77833 Ottersweier
9 * Tel: +19(0)7223/9493-0
10 * Fax: +49(0)7223/9493-92
11 * http://www.addi-data.com
12 * info@addi-data.com
23 * PCI Bar 0 Register map (devpriv->amcc)
28 * PCI Bar 1 Register map (dev->iobase)
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| H A D | amplc_pci230.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * COMEDI - Linux Control and Measurement Device Interface
35 * --------- ---------
43 * The AI subdevice has 16 single-ended channels or 8 differential
46 * The PCI230 and PCI260 cards have 12-bit resolution. The PCI230+ and
47 * PCI260+ cards have 16-bit resolution.
51 * or PCI260 then it actually uses a "pseudo-differential" mode where the
62 * 0 => [-10, +10] V
63 * 1 => [-5, +5] V
64 * 2 => [-2.5, +2.5] V
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| H A D | ni_6527.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Comedi driver for National Instruments PCI-6527
6 * COMEDI - Linux Control and Measurement Device Interface
13 * Devices: [National Instruments] PCI-6527 (pci-6527), PXI-6527 (pxi-6527)
15 * Updated: Sat, 25 Jan 2003 13:24:40 -0800
26 * PCI BAR1 - Register memory map
71 .name = "pci-6527",
74 .name = "pxi-6527",
86 struct ni6527_private *devpriv = dev->private; in ni6527_set_filter_interval()
88 if (val != devpriv->filter_interval) { in ni6527_set_filter_interval()
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| H A D | addi_apci_1032.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
7 * ADDI-DATA GmbH
9 * D-77833 Ottersweier
10 * Tel: +19(0)7223/9493-0
11 * Fax: +49(0)7223/9493-92
12 * http://www.addi-data.com
13 * info@addi-data.com
18 * Description: ADDI-DATA APCI-1032 Digital Input Board
19 * Author: ADDI-DATA GmbH <info@addi-data.com>,
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio-nmk.txt | 4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
15 - gpio-controller : Marks the device node as a GPIO controller.
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| H A D | nvidia,tegra20-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
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| /openbmc/linux/Documentation/arch/arm/ |
| H A D | interrupts.rst | 5 2.5.2-rmk5:
7 major architecture-specific subsystems.
10 MMU TLB. Each MMU TLB variant is now handled completely separately -
21 machine type that we currently have.
26 SA1100 ------------> Neponset -----------> SA1111
28 -----------> USAR
30 -----------> SMC9196
33 exclusive of each other - if you're processing one interrupt from the
36 IDE PIO-based interrupt on the SA1111 excludes all other SA1111 and
37 SMC9196 interrupts until it has finished transferring its multi-sector
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | nvidia,tegra20-gpio.txt | 4 - compatible : "nvidia,tegra<chip>-gpio"
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
9 - #gpio-cells : Should be two. The first cell is the pin number and the
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
12 - gpio-controller : Marks the device node as a GPIO controller.
13 - #interrupt-cells : Should be 2.
16 bits[3:0] trigger type and level flags:
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
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| /openbmc/linux/arch/x86/kernel/apic/ |
| H A D | io_apic.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
25 * - SiS APIC rmw bug:
28 * required to rewrite the index register for a read-modify-write
74 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
113 * Saved state during suspend/resume, or while enabling intr-remap.
146 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; in mp_ioapic_pin_count()
151 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; in mp_pin_to_gsi()
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-ftintc010.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Based on arch/arm/mach-gemini/irq.c
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@gmail.com>
29 /* Selects level- or edge-triggered */
31 /* Selects active low/high or falling/rising edge */
42 * struct ft010_irq_data - irq data container for the Faraday IRQ controller
58 mask = readl(FT010_IRQ_MASK(f->base)); in ft010_irq_mask()
60 writel(mask, FT010_IRQ_MASK(f->base)); in ft010_irq_mask()
68 mask = readl(FT010_IRQ_MASK(f->base)); in ft010_irq_unmask()
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| H A D | irq-meson-gpio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
38 #define REG_EDGE_POL_EDGE(params, x) BIT((params)->edge_single_offset + (x))
39 #define REG_EDGE_POL_LOW(params, x) BIT((params)->pol_low_offset + (x))
40 #define REG_BOTH_EDGE(params, x) BIT((params)->edge_both_offset + (x))
57 unsigned int type, u32 *channel_hwirq);
59 unsigned int type, u32 *channel_hwirq);
66 unsigned int type, u32 *channel_hwirq);
80 #define INIT_MESON_COMMON(irqs, init, sel, type) \ argument
85 .gpio_irq_set_type = type, \
158 { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
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| /openbmc/linux/drivers/iio/adc/ |
| H A D | stm32-dfsdm-adc.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
10 #include <linux/dma-mapping.h>
11 #include <linux/iio/adc/stm32-dfsdm-adc.h>
13 #include <linux/iio/hw-consumer.h>
15 #include <linux/iio/timer/stm32-lptim-trigger.h>
16 #include <linux/iio/timer/stm32-timer-trigger.h>
17 #include <linux/iio/trigger.h>
28 #include "stm32-dfsdm.h"
43 /* Limit filter output resolution to 31 bits. (i.e. sample range is +/-2^30) */
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| /openbmc/linux/include/soc/at91/ |
| H A D | atmel_tcb.h | 17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18 * three general-purpose 16-bit timers. These timers share one register bank.
23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
37 * struct atmel_tcb_config - SoC data for a Timer/Counter Block
50 * struct atmel_tc - information about a Timer/Counter Block
80 /* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
85 * Two registers have block-wide controls. These are: configuring the three
119 * when it's not "external") is silicon-specific. AT91 platforms use one
120 * set of definitions; AVR32 platforms use a different set. Don't hard-wire
130 * PWM output, and TIOB as either another PWM or as a trigger. Capture mode
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