| /openbmc/linux/drivers/memory/ |
| H A D | jedec_ddr_data.c | 42 .tWTR = 10000,
63 .tWTR = 7500,
84 .tWTR = 7500,
105 .tWTR = 7500,
126 .tWTR = 2,
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| H A D | of_memory.c | 43 ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); in of_get_min_tck()
75 ret |= of_property_read_u32(np, "tWTR", &tim->tWTR); in of_do_get_timings()
182 ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); in of_lpddr3_get_min_tck()
228 ret |= of_property_read_u32(np, "tWTR", &tim->tWTR); in of_lpddr3_do_get_timings()
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| H A D | jedec_ddr.h | 155 u32 tWTR; member
179 u32 tWTR; member
235 u32 tWTR; member
264 u32 tWTR; member
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | elpida_ecb240abacn.dtsi | 17 tWTR-min-tck = <2>;
33 tWTR = <7500>;
55 tWTR = <10000>;
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr2.yaml | 56 tWTR-min-tck:
156 tWTR-min-tck = <2>;
172 tWTR = <7500>;
193 tWTR = <10000>;
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| H A D | jedec,lpddr3.yaml | 155 tWTR-min-tck:
216 tWTR-min-tck = <2>;
239 tWTR = <3750>;
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| H A D | jedec,lpddr2-timings.yaml | 82 tWTR:
130 tWTR = <7500>;
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| H A D | jedec,lpddr3-timings.yaml | 109 tWTR:
153 tWTR = <3750>;
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| /openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr2_v3s.c | 16 u8 twtr = max(ns_to_t(8), 2); in mctl_set_timing_params() local
44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in mctl_set_timing_params()
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| H A D | ddr3_1333.c | 16 u8 twtr = max(ns_to_t(8), 4); in mctl_set_timing_params() local
44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 16 u8 twtr = max(ns_to_t(8), 2); in mctl_set_timing_params() local
44 u8 twr2rd = tcwl + 4 + 1 + twtr; in mctl_set_timing_params()
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a83t.c | 98 u8 twtr = max(ns_to_t(8), 4); in auto_set_timing_para() local
127 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para()
150 twtr = max(ns_to_t(8), 2); in auto_set_timing_para()
166 twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para()
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| H A D | dram_sun9i.c | 122 struct dram_sun9i_timing tWTR; member
385 const u32 tWTR = MAX(para->tWTR.ck, PS2CYCLES_ROUNDUP(para->tWTR.ps)); in mctl_channel_init() local
518 #define WR2PRE (MCTL_BL/2 + CWL + tWTR) in mctl_channel_init()
519 /* wr2rd = CWL + BL/2 + tWTR */ in mctl_channel_init()
520 #define WR2RD (MCTL_BL/2 + CWL + tWTR) in mctl_channel_init()
642 (tRCD << 12) | (tRP << 8) | (tWTR << 4) | (tRTP << 0), in mctl_channel_init()
895 .tWTR = { .ck = 4, .ps = 7500 }, in sunxi_dram_init()
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| H A D | dram_sun8i_a33.c | 98 u8 twtr = max(ns_to_t(8), 4); in auto_set_timing_para() local
127 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para()
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| /openbmc/u-boot/include/ |
| H A D | spd.h | 52 unsigned char twtr; /* 37 Int write to read delay tWTR */ member
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| /openbmc/u-boot/doc/device-tree-bindings/misc/ |
| H A D | intel,baytrail-fsp.txt | 84 - fsp,dimm-twtr
147 fsp,dimm-twtr = <6>;
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_rk3036.h | 59 u32 twtr; member
256 u32 twtr; member
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| H A D | sdram.h | 62 u32 twtr; member
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| H A D | ddr_rk3368.h | 63 u32 twtr; member
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| H A D | sdram_rk322x.h | 95 u32 twtr; member
221 u32 twtr; member
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| /openbmc/u-boot/arch/arm/include/asm/arch-vf610/ |
| H A D | ddrmc-vf610.h | 25 u8 twtr; member
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| /openbmc/u-boot/arch/arm/mach-imx/mx6/ |
| H A D | ddr.c | 1000 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr; in mx6_lpddr2_cfg() local
1067 twtr = DIV_ROUND_UP(7500, clkper) - 1; in mx6_lpddr2_cfg()
1093 debug("twtr=%d\n", twtr); in mx6_lpddr2_cfg()
1143 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd; in mx6_lpddr2_cfg()
1231 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; in mx6_ddr3_cfg() local
1338 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1; in mx6_ddr3_cfg()
1340 trtp = twtr; in mx6_ddr3_cfg()
1370 debug("twtr=%d\n", twtr); in mx6_ddr3_cfg()
1437 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd; in mx6_ddr3_cfg()
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| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | emif.c | 61 .tWTR = 2,
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| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | emif.c | 84 .tWTR = 2,
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| /openbmc/u-boot/board/olimex/mx23_olinuxino/ |
| H A D | spl_boot.c | 108 /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */ in mxs_adjust_memory_params()
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