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/openbmc/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi91 clocks = <&sysclk K210_CLK_SRAM0>,
92 <&sysclk K210_CLK_SRAM1>,
93 <&sysclk K210_CLK_AI>;
139 clocks = <&sysclk K210_CLK_CPU>;
162 clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
179 clocks = <&sysclk K210_CLK_APB0>;
186 clocks = <&sysclk K210_CLK_APB0>,
187 <&sysclk K210_CLK_GPIO>;
207 clocks = <&sysclk K210_CLK_UART1>,
208 <&sysclk K210_CLK_APB0>;
[all …]
/openbmc/linux/arch/powerpc/boot/
H A Dmpc8xx.c55 void mpc8xx_set_clocks(u32 sysclk) in mpc8xx_set_clocks() argument
59 dt_fixup_cpu_clocks(sysclk, sysclk / 16, sysclk); in mpc8xx_set_clocks()
63 setprop(node, "clock-frequency", &sysclk, 4); in mpc8xx_set_clocks()
67 setprop(node, "clock-frequency", &sysclk, 4); in mpc8xx_set_clocks()
72 u32 sysclk = mpc885_get_clock(crystal); in mpc885_fixup_clocks() local
73 if (!sysclk) in mpc885_fixup_clocks()
76 mpc8xx_set_clocks(sysclk); in mpc885_fixup_clocks()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqoriq-clock.txt4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
64 - clock-frequency: Input system clock frequency (SYSCLK)
65 - clocks: If clock-frequency is not specified, sysclk may be provided
72 "sysclk" and "coreclk".
84 0 sysclk must be 0
121 * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
123 * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
128 clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
154 sysclk: sysclk {
156 compatible = "fsl,qoriq-sysclk-1.0";
[all …]
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32h7.c590 static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk, in stm32_get_timer_rate() argument
605 return sysclk; in stm32_get_timer_rate()
607 return sysclk / 2; in stm32_get_timer_rate()
609 return sysclk / 4; in stm32_get_timer_rate()
617 return sysclk; in stm32_get_timer_rate()
622 return sysclk / psc; in stm32_get_timer_rate()
633 ulong sysclk = 0; in stm32_clk_get_rate() local
647 sysclk = stm32_get_PLL1_rate(regs, PLL1_P_CK); in stm32_clk_get_rate()
650 sysclk = stm32_get_rate(regs, HSE); in stm32_clk_get_rate()
654 sysclk = stm32_get_rate(regs, CSI); in stm32_clk_get_rate()
[all …]
/openbmc/u-boot/doc/
H A DREADME.mpc85xxcds150 XXXX1000 == CCB:SYSCLK 8:1
151 XXXX1010 == CCB:SYSCLK 10:1
184 XXXX0000 == CCB:SYSCLK 16:1
186 XXXX0010 == CCB:SYSCLK 2:1
187 XXXX0011 == CCB:SYSCLK 3:1
188 XXXX0100 == CCB:SYSCLK 4:1
189 XXXX0101 == CCB:SYSCLK 5:1
190 XXXX0110 == CCB:SYSCLK 6:1
192 XXXX1000 == CCB:SYSCLK 8:1
193 XXXX1001 == CCB:SYSCLK 9:1
[all …]
/openbmc/qemu/hw/arm/
H A Dnetduino2.c34 /* Main SYSCLK frequency in Hz (120MHz) */
40 Clock *sysclk; in netduino2_init() local
43 sysclk = clock_new(OBJECT(machine), "SYSCLK"); in netduino2_init()
44 clock_set_hz(sysclk, SYSCLK_FRQ); in netduino2_init()
48 qdev_connect_clock_in(dev, "sysclk", sysclk); in netduino2_init()
H A Dnetduinoplus2.c34 /* Main SYSCLK frequency in Hz (168MHz) */
40 Clock *sysclk; in netduinoplus2_init() local
43 sysclk = clock_new(OBJECT(machine), "SYSCLK"); in netduinoplus2_init()
44 clock_set_hz(sysclk, SYSCLK_FRQ); in netduinoplus2_init()
48 qdev_connect_clock_in(dev, "sysclk", sysclk); in netduinoplus2_init()
H A Dstm32vldiscovery.c37 /* Main SYSCLK frequency in Hz (24MHz) */
43 Clock *sysclk; in stm32vldiscovery_init() local
46 sysclk = clock_new(OBJECT(machine), "SYSCLK"); in stm32vldiscovery_init()
47 clock_set_hz(sysclk, SYSCLK_FRQ); in stm32vldiscovery_init()
51 qdev_connect_clock_in(dev, "sysclk", sysclk); in stm32vldiscovery_init()
H A Dolimex-stm32-h405.c37 /* Main SYSCLK frequency in Hz (168MHz) */
43 Clock *sysclk; in olimex_stm32_h405_init() local
46 sysclk = clock_new(OBJECT(machine), "SYSCLK"); in olimex_stm32_h405_init()
47 clock_set_hz(sysclk, SYSCLK_FRQ); in olimex_stm32_h405_init()
51 qdev_connect_clock_in(dev, "sysclk", sysclk); in olimex_stm32_h405_init()
H A Dstm32f100_soc.c62 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in stm32f100_soc_initfn()
85 if (!clock_has_source(s->sysclk)) { in stm32f100_soc_realize()
86 error_setg(errp, "sysclk clock must be wired up by the board code"); in stm32f100_soc_realize()
92 * change the sysclk frequency and define different sysclk sources. in stm32f100_soc_realize()
97 clock_set_source(s->refclk, s->sysclk); in stm32f100_soc_realize()
121 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); in stm32f100_soc_realize()
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dintegratorap-im-pd1.dts41 clocks = <&sysclk>;
51 clocks = <&sysclk>;
169 clocks = <&impd1_uartclk>, <&sysclk>;
177 clocks = <&impd1_uartclk>, <&sysclk>;
185 clocks = <&impd1_sspclk>, <&sysclk>;
197 clocks = <&sysclk>;
209 clocks = <&sysclk>;
217 clocks = <&sysclk>;
226 clocks = <&sysclk>, <&sysclk>;
239 clocks = <&sysclk>;
[all …]
H A Dmps2.dtsi81 sysclk: clk-sys { label
151 clocks = <&sysclk>;
159 clocks = <&sysclk>;
166 clocks = <&sysclk>, <&sysclk>, <&sysclk>;
177 clocks = <&sysclk>;
185 clocks = <&sysclk>;
193 clocks = <&sysclk>;
202 clocks = <&sysclk>, <&sysclk>;
/openbmc/linux/sound/soc/ti/
H A Ddavinci-evm.c26 unsigned sysclk; member
60 unsigned sysclk = ((struct snd_soc_card_drvdata_davinci *) in evm_hw_params() local
61 snd_soc_card_get_drvdata(soc_card))->sysclk; in evm_hw_params()
64 ret = snd_soc_dai_set_sysclk(codec_dai, 0, sysclk, SND_SOC_CLOCK_OUT); in evm_hw_params()
69 ret = snd_soc_dai_set_sysclk(cpu_dai, 0, sysclk, SND_SOC_CLOCK_OUT); in evm_hw_params()
223 ret = of_property_read_u32(np, "ti,codec-clock-rate", &drvdata->sysclk); in davinci_evm_probe()
231 drvdata->sysclk = clk_get_rate(drvdata->mclk); in davinci_evm_probe()
233 unsigned int requestd_rate = drvdata->sysclk; in davinci_evm_probe()
234 clk_set_rate(drvdata->mclk, drvdata->sysclk); in davinci_evm_probe()
235 drvdata->sysclk = clk_get_rate(drvdata->mclk); in davinci_evm_probe()
[all …]
/openbmc/linux/drivers/clk/davinci/
H A Dpll-da850.c49 SYSCLK(1, pll0_sysclk1, pll0_pllen, 5, SYSCLK_FIXED_DIV);
50 SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
51 SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
52 SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
53 SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
54 SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_ARM_RATE | SYSCLK_FIXED_DIV);
55 SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
172 SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
173 SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, 0);
174 SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, 0);
H A Dpll-da830.c33 SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
34 SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
35 SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
36 SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
37 SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
38 SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
/openbmc/linux/arch/powerpc/platforms/83xx/
H A Dmpc832x_rdb.c41 static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk, in of_fsl_spi_probe() argument
62 pdata.sysclk = sysclk; in of_fsl_spi_probe()
127 u32 sysclk = -1; in fsl_spi_init() local
131 sysclk = get_brgfreq(); in fsl_spi_init()
132 if (sysclk == -1) { in fsl_spi_init()
133 sysclk = fsl_get_sys_freq(); in fsl_spi_init()
134 if (sysclk == -1) in fsl_spi_init()
138 ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos, in fsl_spi_init()
141 of_fsl_spi_probe("spi", "fsl_spi", sysclk, board_infos, in fsl_spi_init()
/openbmc/linux/sound/soc/codecs/
H A Dwm8960.c143 int sysclk; member
622 * wm8960_configure_sysclk - checks if there is a sysclk frequency available
623 * The sysclk must be chosen such that:
624 * - sysclk = MCLK / sysclk_divs
625 * - lrclk = sysclk / dac_divs
626 * - 10 * bclk = sysclk / bclk_divs
629 * @mclk: MCLK used to derive sysclk
630 * @sysclk_idx: sysclk_divs index for found sysclk
635 * -1, in case no sysclk frequency available found
636 * >=0, in case we could derive bclk and lrclk from sysclk using
[all …]
H A Dwm8998.c503 SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1,
914 { "OUT1L", NULL, "SYSCLK" },
915 { "OUT1R", NULL, "SYSCLK" },
916 { "OUT2L", NULL, "SYSCLK" },
917 { "OUT2R", NULL, "SYSCLK" },
918 { "OUT3", NULL, "SYSCLK" },
919 { "OUT4L", NULL, "SYSCLK" },
920 { "OUT4R", NULL, "SYSCLK" },
921 { "OUT5L", NULL, "SYSCLK" },
922 { "OUT5R", NULL, "SYSCLK" },
[all …]
H A Dwm5100.c61 int sysclk; member
132 if ((wm5100->sysclk % rate) == 0) { in wm5100_alloc_sr()
168 "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n", in wm5100_alloc_sr()
169 rate, wm5100->sysclk, wm5100->asyncclk); in wm5100_alloc_sr()
799 dev_crit(wm5100->dev, "SYSCLK underclocked\n"); in wm5100_log_status3()
857 SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
1085 { "IN1L", NULL, "SYSCLK" },
1086 { "IN1R", NULL, "SYSCLK" },
1087 { "IN2L", NULL, "SYSCLK" },
1088 { "IN2R", NULL, "SYSCLK" },
[all …]
/openbmc/u-boot/board/freescale/common/
H A Dngpixis.c155 void pixis_sysclk_set(unsigned long sysclk) in pixis_sysclk_set() argument
160 freq_word = ics307_sysclk_calculator(sysclk); in pixis_sysclk_set()
165 /* set SYSCLK enable bit */ in pixis_sysclk_set()
168 /* SYSCLK to required frequency */ in pixis_sysclk_set()
177 unsigned long sysclk; in pixis_reset_cmd() local
201 if (strcmp(argv[i], "sysclk") == 0) { in pixis_reset_cmd()
202 sysclk = simple_strtoul(argv[i + 1], NULL, 0); in pixis_reset_cmd()
204 pixis_sysclk_set(sysclk); in pixis_reset_cmd()
243 "pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n";
/openbmc/linux/sound/soc/xilinx/
H A Dxlnx_i2s.c30 unsigned int sysclk; member
46 drv_data->sysclk = 0; in xlnx_i2s_set_sclkout_div()
58 drv_data->sysclk = freq; in xlnx_i2s_set_sysclk()
82 if (drv_data->sysclk) in xlnx_i2s_startup()
97 if (drv_data->sysclk) { in xlnx_i2s_hw_params()
106 sclk_div = drv_data->sysclk / sclk / 2; in xlnx_i2s_hw_params()
108 if ((drv_data->sysclk % sclk != 0) || in xlnx_i2s_hw_params()
110 dev_warn(i2s_dai->dev, "invalid SCLK divisor for sysclk %u and sclk %u\n", in xlnx_i2s_hw_params()
111 drv_data->sysclk, sclk); in xlnx_i2s_hw_params()
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-ls1043a.dtsi16 sysclk: sysclk { label
20 clock-output-names = "sysclk";
44 clocks = <&sysclk>;
163 clocks = <&sysclk>;
172 clocks = <&sysclk>;
182 clocks = <&sysclk>;
190 clocks = <&sysclk>;
199 clocks = <&sysclk>;
208 clocks = <&sysclk>;
/openbmc/linux/sound/soc/meson/
H A Daxg-pdm.c95 struct clk *sysclk; member
176 return clk_set_rate(priv->sysclk, sys_rate); in axg_pdm_set_sysclk()
178 return clk_set_rate(priv->sysclk, priv->cfg->sys_rate); in axg_pdm_set_sysclk()
187 spmax = DIV_ROUND_UP_ULL((u64)clk_get_rate(priv->sysclk), in axg_pdm_set_sample_pointer()
190 /* Check if sysclk is not too fast - should not happen */ in axg_pdm_set_sample_pointer()
386 * sysclk must be set and enabled as well to access the pdm registers in axg_pdm_dai_probe()
389 ret = clk_set_rate(priv->sysclk, priv->cfg->sys_rate); in axg_pdm_dai_probe()
391 dev_err(dai->dev, "setting sysclk failed\n"); in axg_pdm_dai_probe()
395 ret = clk_prepare_enable(priv->sysclk); in axg_pdm_dai_probe()
397 dev_err(dai->dev, "enabling sysclk failed\n"); in axg_pdm_dai_probe()
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-fsl-lib.c101 mpc8xxx_spi->spibrg = pdata->sysclk; in mpc8xxx_spi_probe()
135 pdata->sysclk = get_brgfreq(); in of_mpc8xxx_spi_probe()
136 if (pdata->sysclk == -1) { in of_mpc8xxx_spi_probe()
137 pdata->sysclk = fsl_get_sys_freq(); in of_mpc8xxx_spi_probe()
138 if (pdata->sysclk == -1) in of_mpc8xxx_spi_probe()
142 ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk); in of_mpc8xxx_spi_probe()
/openbmc/linux/sound/soc/loongson/
H A Dloongson_i2s.c66 u32 sysclk = i2s->sysclk; in loongson_i2s_hw_params() local
78 mclk_ratio = DIV_ROUND_CLOSEST(clk_rate, (sysclk * 2)) - 1; in loongson_i2s_hw_params()
89 bclk_ratio = DIV_ROUND_CLOSEST(sysclk, in loongson_i2s_hw_params()
91 mclk_ratio = clk_rate / sysclk; in loongson_i2s_hw_params()
93 sysclk) - (mclk_ratio << 16); in loongson_i2s_hw_params()
121 i2s->sysclk = freq; in loongson_i2s_set_dai_sysclk()

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