xref: /openbmc/qemu/hw/arm/olimex-stm32-h405.c (revision f614acb7450282a119d85d759f27eae190476058)
1ee5bffa9SFelipe Balbi /*
2ee5bffa9SFelipe Balbi  * ST STM32VLDISCOVERY machine
3ee5bffa9SFelipe Balbi  * Olimex STM32-H405 machine
4ee5bffa9SFelipe Balbi  *
5ee5bffa9SFelipe Balbi  * Copyright (c) 2022 Felipe Balbi <balbi@kernel.org>
6ee5bffa9SFelipe Balbi  *
7ee5bffa9SFelipe Balbi  * Permission is hereby granted, free of charge, to any person obtaining a copy
8ee5bffa9SFelipe Balbi  * of this software and associated documentation files (the "Software"), to deal
9ee5bffa9SFelipe Balbi  * in the Software without restriction, including without limitation the rights
10ee5bffa9SFelipe Balbi  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11ee5bffa9SFelipe Balbi  * copies of the Software, and to permit persons to whom the Software is
12ee5bffa9SFelipe Balbi  * furnished to do so, subject to the following conditions:
13ee5bffa9SFelipe Balbi  *
14ee5bffa9SFelipe Balbi  * The above copyright notice and this permission notice shall be included in
15ee5bffa9SFelipe Balbi  * all copies or substantial portions of the Software.
16ee5bffa9SFelipe Balbi  *
17ee5bffa9SFelipe Balbi  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18ee5bffa9SFelipe Balbi  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19ee5bffa9SFelipe Balbi  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20ee5bffa9SFelipe Balbi  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21ee5bffa9SFelipe Balbi  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22ee5bffa9SFelipe Balbi  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23ee5bffa9SFelipe Balbi  * THE SOFTWARE.
24ee5bffa9SFelipe Balbi  */
25ee5bffa9SFelipe Balbi 
26ee5bffa9SFelipe Balbi #include "qemu/osdep.h"
27ee5bffa9SFelipe Balbi #include "qapi/error.h"
28ee5bffa9SFelipe Balbi #include "hw/boards.h"
29ee5bffa9SFelipe Balbi #include "hw/qdev-properties.h"
30ee5bffa9SFelipe Balbi #include "hw/qdev-clock.h"
31ee5bffa9SFelipe Balbi #include "qemu/error-report.h"
32ee5bffa9SFelipe Balbi #include "hw/arm/stm32f405_soc.h"
33ee5bffa9SFelipe Balbi #include "hw/arm/boot.h"
34ee5bffa9SFelipe Balbi 
35ee5bffa9SFelipe Balbi /* olimex-stm32-h405 implementation is derived from netduinoplus2 */
36ee5bffa9SFelipe Balbi 
37ee5bffa9SFelipe Balbi /* Main SYSCLK frequency in Hz (168MHz) */
38ee5bffa9SFelipe Balbi #define SYSCLK_FRQ 168000000ULL
39ee5bffa9SFelipe Balbi 
olimex_stm32_h405_init(MachineState * machine)40ee5bffa9SFelipe Balbi static void olimex_stm32_h405_init(MachineState *machine)
41ee5bffa9SFelipe Balbi {
42ee5bffa9SFelipe Balbi     DeviceState *dev;
43ee5bffa9SFelipe Balbi     Clock *sysclk;
44ee5bffa9SFelipe Balbi 
45ee5bffa9SFelipe Balbi     /* This clock doesn't need migration because it is fixed-frequency */
46ee5bffa9SFelipe Balbi     sysclk = clock_new(OBJECT(machine), "SYSCLK");
47ee5bffa9SFelipe Balbi     clock_set_hz(sysclk, SYSCLK_FRQ);
48ee5bffa9SFelipe Balbi 
49ee5bffa9SFelipe Balbi     dev = qdev_new(TYPE_STM32F405_SOC);
50*f503bc4bSPhilippe Mathieu-Daudé     object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
51ee5bffa9SFelipe Balbi     qdev_connect_clock_in(dev, "sysclk", sysclk);
52ee5bffa9SFelipe Balbi     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
53ee5bffa9SFelipe Balbi 
54ee5bffa9SFelipe Balbi     armv7m_load_kernel(ARM_CPU(first_cpu),
55ee5bffa9SFelipe Balbi                        machine->kernel_filename,
56ee5bffa9SFelipe Balbi                        0, FLASH_SIZE);
57ee5bffa9SFelipe Balbi }
58ee5bffa9SFelipe Balbi 
olimex_stm32_h405_machine_init(MachineClass * mc)59ee5bffa9SFelipe Balbi static void olimex_stm32_h405_machine_init(MachineClass *mc)
60ee5bffa9SFelipe Balbi {
61e1b72c55SPhilippe Mathieu-Daudé     static const char * const valid_cpu_types[] = {
62e1b72c55SPhilippe Mathieu-Daudé         ARM_CPU_TYPE_NAME("cortex-m4"),
63e1b72c55SPhilippe Mathieu-Daudé         NULL
64e1b72c55SPhilippe Mathieu-Daudé     };
65e1b72c55SPhilippe Mathieu-Daudé 
66ee5bffa9SFelipe Balbi     mc->desc = "Olimex STM32-H405 (Cortex-M4)";
67ee5bffa9SFelipe Balbi     mc->init = olimex_stm32_h405_init;
68e1b72c55SPhilippe Mathieu-Daudé     mc->valid_cpu_types = valid_cpu_types;
69ee5bffa9SFelipe Balbi 
70ee5bffa9SFelipe Balbi     /* SRAM pre-allocated as part of the SoC instantiation */
71ee5bffa9SFelipe Balbi     mc->default_ram_size = 0;
72ee5bffa9SFelipe Balbi }
73ee5bffa9SFelipe Balbi 
74ee5bffa9SFelipe Balbi DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init)
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