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/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml91 sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
101 spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
131 signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
171 sdmmc1_3v3: sdmmc1-3v3 {
172 pins = "sdmmc1-hv";
176 sdmmc1_1v8: sdmmc1-1v8 {
177 pins = "sdmmc1-hv";
182 sdmmc1: mmc@3400000 {
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32f7-pinctrl.dtsi237 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
238 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
239 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
240 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
241 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
242 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
250 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
251 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
252 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
253 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
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H A Dstm32h7-pinctrl.dtsi72 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
86 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
105 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
116 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
131 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
H A Dstm32mp13-pinctrl.dtsi117 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
130 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
148 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
159 sdmmc1_clk_pins_a: sdmmc1-clk-0 {
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dpinmux.c25 PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3),
26 PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3),
27 PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3),
28 PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3),
29 PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3),
30 PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3),
188 PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3),
191 PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3),
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dpinmux.c43 PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
44 PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
45 PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
46 PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
47 PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
48 PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
123 PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, SPI4),
226 PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC1, RSVD4),
281 PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drv1126-pinctrl.dtsi160 sdmmc1 {
162 sdmmc1_bus4: sdmmc1-bus4 {
174 sdmmc1_clk: sdmmc1-clk {
180 sdmmc1_cmd: sdmmc1-cmd {
186 sdmmc1_det: sdmmc1-det {
191 sdmmc1_pwr: sdmmc1-pwr {
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dpinmux.c43 PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
44 PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
45 PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
46 PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
47 PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
48 PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
123 PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, GMI),
283 PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
/openbmc/u-boot/board/nvidia/cardhu/
H A Dpinmux-config-cardhu.h58 /* SDMMC1 pinmux */
59 DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
60 DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
61 DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
62 DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
63 DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
64 DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
281 /* SDMMC1 CD gpio */
283 /* SDMMC1 WP gpio */
/openbmc/u-boot/board/nvidia/p2371-2180/
H A Dpinmux-config-p2371-2180.h176 PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
177 PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
178 PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
179 PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
180 PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
181 PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
225 PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
228 PINCFG(PZ4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
/openbmc/u-boot/board/nvidia/dalmore/
H A Dpinmux-config-dalmore.h164 /* SDMMC1 pinmux */
165 DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
166 DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
167 DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
168 DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
169 DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
170 DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
/openbmc/u-boot/board/nvidia/p2571/
H A Dpinmux-config-p2571.h140 PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
141 PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
142 PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
143 PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
144 PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
145 PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
189 PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
/openbmc/u-boot/board/nvidia/p2371-0000/
H A Dpinmux-config-p2371-0000.h165 PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
166 PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
167 PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
168 PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
169 PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
170 PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
214 PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
/openbmc/u-boot/board/nvidia/e2220-1170/
H A Dpinmux-config-e2220-1170.h174 PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
175 PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
176 PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
177 PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
178 PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
179 PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
223 PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
/openbmc/u-boot/board/avionic-design/common/
H A Dpinmux-config-tamonten-ng.h59 /* SDMMC1 pinmux */
60 DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
61 DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
62 DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
63 DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
64 DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
65 DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
/openbmc/u-boot/board/toradex/apalis_t30/
H A Dpinmux-config-apalis_t30.h58 /* SDMMC1 pinmux */
59 DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
60 DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, NORMAL, NORMAL, INPUT),
61 DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, NORMAL, NORMAL, INPUT),
62 DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, NORMAL, NORMAL, INPUT),
63 DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, NORMAL, NORMAL, INPUT),
64 DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, NORMAL, NORMAL, INPUT),
/openbmc/u-boot/board/nvidia/nyan-big/
H A Dpinmux-config-nyan-big.h206 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
227 PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
228 PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
229 PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
230 PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
231 PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
232 PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
/openbmc/u-boot/board/toradex/apalis-tk1/
H A Dpinmux-config-apalis-tk1.h191 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
212 PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
213 PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
214 PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
215 PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
216 PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
217 PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
/openbmc/u-boot/board/nvidia/venice2/
H A Dpinmux-config-venice2.h217 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
238 PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
239 PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
240 PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
241 PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
242 PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
243 PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dpinmux.c43 PIN(SDMMC1_CLK_PZ0, SDMMC1, RSVD2, RSVD3, UARTA),
44 PIN(SDMMC1_CMD_PZ1, SDMMC1, RSVD2, RSVD3, UARTA),
45 PIN(SDMMC1_DAT3_PY4, SDMMC1, RSVD2, UARTE, UARTA),
46 PIN(SDMMC1_DAT2_PY5, SDMMC1, RSVD2, UARTE, UARTA),
47 PIN(SDMMC1_DAT1_PY6, SDMMC1, RSVD2, UARTE, UARTA),
48 PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, UARTE, UARTA),
/openbmc/u-boot/arch/arm/dts/
H A Dstm32h743i-disco.dts63 mmc0 = &sdmmc1;
103 &sdmmc1 {
H A Dstm32mp157c-ed1-u-boot.dtsi12 mmc0 = &sdmmc1;
184 &sdmmc1 {
H A Dstm32h743.dtsi125 sdmmc1: sdmmc@52007000 { label
130 resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32f.c190 /* select 48MHz as SDMMC1 clock source */ in configure_clocks()
203 /* select 48MHz as SDMMC1 clock source */ in configure_clocks()
446 * particular case for SDMMC1 and SDMMC2 : in stm32_clk_get_rate()
450 case STM32F7_APB2_CLOCK(SDMMC1): in stm32_clk_get_rate()
452 if (clk->id == STM32F7_APB2_CLOCK(SDMMC1)) in stm32_clk_get_rate()
458 /* System clock is selected as SDMMC1 clock */ in stm32_clk_get_rate()
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-apalis-v1.2.dtsi341 sdmmc1-cd-n-pv3 { /* CD# GPIO */
343 nvidia,function = "sdmmc1";
355 sdmmc1-dat3-py4 {
357 nvidia,function = "sdmmc1";
362 sdmmc1-dat2-py5 {
364 nvidia,function = "sdmmc1";
369 sdmmc1-dat1-py6 {
371 nvidia,function = "sdmmc1";
376 sdmmc1-dat0-py7 {
378 nvidia,function = "sdmmc1";
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