183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2bf78b271SMarcel Ziswiler /* 3bf78b271SMarcel Ziswiler * Copyright (c) 2014, Marcel Ziswiler 4bf78b271SMarcel Ziswiler */ 5bf78b271SMarcel Ziswiler 6bf78b271SMarcel Ziswiler #ifndef _PINMUX_CONFIG_APALIS_T30_H_ 7bf78b271SMarcel Ziswiler #define _PINMUX_CONFIG_APALIS_T30_H_ 8bf78b271SMarcel Ziswiler 9bf78b271SMarcel Ziswiler #define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ 10bf78b271SMarcel Ziswiler { \ 11bf78b271SMarcel Ziswiler .pingrp = PMUX_PINGRP_##_pingrp, \ 12bf78b271SMarcel Ziswiler .func = PMUX_FUNC_##_mux, \ 13bf78b271SMarcel Ziswiler .pull = PMUX_PULL_##_pull, \ 14bf78b271SMarcel Ziswiler .tristate = PMUX_TRI_##_tri, \ 15bf78b271SMarcel Ziswiler .io = PMUX_PIN_##_io, \ 16bf78b271SMarcel Ziswiler .lock = PMUX_PIN_LOCK_DEFAULT, \ 17bf78b271SMarcel Ziswiler .od = PMUX_PIN_OD_DEFAULT, \ 18bf78b271SMarcel Ziswiler .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 19bf78b271SMarcel Ziswiler } 20bf78b271SMarcel Ziswiler 21bf78b271SMarcel Ziswiler #define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ 22bf78b271SMarcel Ziswiler { \ 23bf78b271SMarcel Ziswiler .pingrp = PMUX_PINGRP_##_pingrp, \ 24bf78b271SMarcel Ziswiler .func = PMUX_FUNC_##_mux, \ 25bf78b271SMarcel Ziswiler .pull = PMUX_PULL_##_pull, \ 26bf78b271SMarcel Ziswiler .tristate = PMUX_TRI_##_tri, \ 27bf78b271SMarcel Ziswiler .io = PMUX_PIN_##_io, \ 28bf78b271SMarcel Ziswiler .lock = PMUX_PIN_LOCK_##_lock, \ 29bf78b271SMarcel Ziswiler .od = PMUX_PIN_OD_##_od, \ 30bf78b271SMarcel Ziswiler .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 31bf78b271SMarcel Ziswiler } 32bf78b271SMarcel Ziswiler 33bf78b271SMarcel Ziswiler #define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ 34bf78b271SMarcel Ziswiler { \ 35bf78b271SMarcel Ziswiler .pingrp = PMUX_PINGRP_##_pingrp, \ 36bf78b271SMarcel Ziswiler .func = PMUX_FUNC_##_mux, \ 37bf78b271SMarcel Ziswiler .pull = PMUX_PULL_##_pull, \ 38bf78b271SMarcel Ziswiler .tristate = PMUX_TRI_##_tri, \ 39bf78b271SMarcel Ziswiler .io = PMUX_PIN_##_io, \ 40bf78b271SMarcel Ziswiler .lock = PMUX_PIN_LOCK_##_lock, \ 41bf78b271SMarcel Ziswiler .od = PMUX_PIN_OD_DEFAULT, \ 42bf78b271SMarcel Ziswiler .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ 43bf78b271SMarcel Ziswiler } 44bf78b271SMarcel Ziswiler 45bf78b271SMarcel Ziswiler #define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ 46bf78b271SMarcel Ziswiler { \ 47bf78b271SMarcel Ziswiler .drvgrp = PMUX_DRVGRP_##_drvgrp, \ 48bf78b271SMarcel Ziswiler .slwf = _slwf, \ 49bf78b271SMarcel Ziswiler .slwr = _slwr, \ 50bf78b271SMarcel Ziswiler .drvup = _drvup, \ 51bf78b271SMarcel Ziswiler .drvdn = _drvdn, \ 52bf78b271SMarcel Ziswiler .lpmd = PMUX_LPMD_##_lpmd, \ 53bf78b271SMarcel Ziswiler .schmt = PMUX_SCHMT_##_schmt, \ 54bf78b271SMarcel Ziswiler .hsm = PMUX_HSM_##_hsm, \ 55bf78b271SMarcel Ziswiler } 56bf78b271SMarcel Ziswiler 57bf78b271SMarcel Ziswiler static struct pmux_pingrp_config tegra3_pinmux_common[] = { 58bf78b271SMarcel Ziswiler /* SDMMC1 pinmux */ 59bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), 60bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, NORMAL, NORMAL, INPUT), 61bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, NORMAL, NORMAL, INPUT), 62bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, NORMAL, NORMAL, INPUT), 63bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, NORMAL, NORMAL, INPUT), 64bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, NORMAL, NORMAL, INPUT), 65bf78b271SMarcel Ziswiler 66bf78b271SMarcel Ziswiler /* SDMMC3 pinmux */ 67bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), 68bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, NORMAL, INPUT), 69bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, NORMAL, NORMAL, INPUT), 70bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, NORMAL, NORMAL, INPUT), 71bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, NORMAL, NORMAL, INPUT), 72bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, NORMAL, NORMAL, INPUT), 73bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, NORMAL, INPUT), 74bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, NORMAL, INPUT), 75bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, NORMAL, INPUT), 76bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, NORMAL, NORMAL, INPUT), 77bf78b271SMarcel Ziswiler 78bf78b271SMarcel Ziswiler /* SDMMC4 pinmux (eMMC) */ 79bf78b271SMarcel Ziswiler LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 80bf78b271SMarcel Ziswiler LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 81bf78b271SMarcel Ziswiler LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 82bf78b271SMarcel Ziswiler LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 83bf78b271SMarcel Ziswiler LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 84bf78b271SMarcel Ziswiler LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 85bf78b271SMarcel Ziswiler LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 86bf78b271SMarcel Ziswiler LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 87bf78b271SMarcel Ziswiler LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 88bf78b271SMarcel Ziswiler LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 89bf78b271SMarcel Ziswiler LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), 90bf78b271SMarcel Ziswiler 91bf78b271SMarcel Ziswiler /* I2C1 pinmux */ 92bf78b271SMarcel Ziswiler I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 93bf78b271SMarcel Ziswiler I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 94bf78b271SMarcel Ziswiler 95bf78b271SMarcel Ziswiler /* I2C2 pinmux */ 969a50b6fcSMarcel Ziswiler I2C_PINMUX(GEN2_I2C_SCL_PT5, RSVD3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), 979a50b6fcSMarcel Ziswiler I2C_PINMUX(GEN2_I2C_SDA_PT6, RSVD3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), 98bf78b271SMarcel Ziswiler 99bf78b271SMarcel Ziswiler /* I2C3 pinmux */ 100bf78b271SMarcel Ziswiler I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE), 101bf78b271SMarcel Ziswiler I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE), 102bf78b271SMarcel Ziswiler 103bf78b271SMarcel Ziswiler /* I2C4 pinmux */ 104bf78b271SMarcel Ziswiler I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 105bf78b271SMarcel Ziswiler I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 106bf78b271SMarcel Ziswiler 107bf78b271SMarcel Ziswiler /* Power I2C pinmux */ 108bf78b271SMarcel Ziswiler I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 109bf78b271SMarcel Ziswiler I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 110bf78b271SMarcel Ziswiler 111bf78b271SMarcel Ziswiler DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), 112bf78b271SMarcel Ziswiler /* UARTA RX, make sure we don't get input form a floating Pin */ 113bf78b271SMarcel Ziswiler DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, NORMAL, INPUT), 114bf78b271SMarcel Ziswiler DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), 115bf78b271SMarcel Ziswiler DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT), 116bf78b271SMarcel Ziswiler DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), 117bf78b271SMarcel Ziswiler DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT), 118bf78b271SMarcel Ziswiler DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), 119bf78b271SMarcel Ziswiler DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT), 120bf78b271SMarcel Ziswiler DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT), 121bf78b271SMarcel Ziswiler DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT), 122bf78b271SMarcel Ziswiler DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT), 123bf78b271SMarcel Ziswiler DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT), 124bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), 125bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), 126bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), 127bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), 128bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, INPUT), 129bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, INPUT), 130bf78b271SMarcel Ziswiler DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), 131bf78b271SMarcel Ziswiler DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), 132bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ 133bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ 134bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT), 135bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT), 136bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ 137bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT), 138bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ 139bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT), 140bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ 141bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), 142bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), 143bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), 144bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), 145bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), 146bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), 147bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), 148bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), 149bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), 150bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), 151bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), 152bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), 153bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), 154bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), 155bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), 156bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), 157bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), 158bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), 159bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), 160bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), 161bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), 162bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), 163bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), 164bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), 165bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), 166bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), 167bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), 168bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), 169bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ 170bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ 171bf78b271SMarcel Ziswiler DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), 172bf78b271SMarcel Ziswiler DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), 173bf78b271SMarcel Ziswiler DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), 174bf78b271SMarcel Ziswiler LV_PINMUX(VI_D0_PT4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 175bf78b271SMarcel Ziswiler LV_PINMUX(VI_D1_PD5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 176bf78b271SMarcel Ziswiler LV_PINMUX(VI_D2_PL0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 177bf78b271SMarcel Ziswiler LV_PINMUX(VI_D3_PL1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 178bf78b271SMarcel Ziswiler LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 179bf78b271SMarcel Ziswiler LV_PINMUX(VI_D5_PL3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 180bf78b271SMarcel Ziswiler LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 181bf78b271SMarcel Ziswiler LV_PINMUX(VI_D7_PL5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 182bf78b271SMarcel Ziswiler LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 183bf78b271SMarcel Ziswiler LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 184bf78b271SMarcel Ziswiler LV_PINMUX(VI_D10_PT2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 185bf78b271SMarcel Ziswiler LV_PINMUX(VI_D11_PT3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 186bf78b271SMarcel Ziswiler LV_PINMUX(VI_HSYNC_PD7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 187bf78b271SMarcel Ziswiler LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), 188bf78b271SMarcel Ziswiler LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 189bf78b271SMarcel Ziswiler LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 190bf78b271SMarcel Ziswiler DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), 191bf78b271SMarcel Ziswiler DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), 192bf78b271SMarcel Ziswiler DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ 193bf78b271SMarcel Ziswiler DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ 194bf78b271SMarcel Ziswiler DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), 195bf78b271SMarcel Ziswiler DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), 196bf78b271SMarcel Ziswiler DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), 197bf78b271SMarcel Ziswiler DEFAULT_PINMUX(UART3_RTS_N_PC0, PWM0, NORMAL, NORMAL, OUTPUT), 198bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PU0, RSVD1, DOWN, TRISTATE, OUTPUT), 199bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PU1, RSVD1, DOWN, TRISTATE, OUTPUT), 200bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PU2, RSVD1, DOWN, TRISTATE, OUTPUT), 201bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PU3, PWM0, NORMAL, NORMAL, OUTPUT), 202bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT), 203bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT), 204bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PU6, PWM3, NORMAL, NORMAL, OUTPUT), 205bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ 206bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ 207bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ 208bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ 209bf78b271SMarcel Ziswiler DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, DOWN, TRISTATE, OUTPUT), /* NC */ 210bf78b271SMarcel Ziswiler DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, DOWN, TRISTATE, OUTPUT), /* NC */ 211bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, DOWN, TRISTATE, OUTPUT), /* NC */ 212bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */ 213bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, DOWN, TRISTATE, OUTPUT), /* NC */ 214bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD10_PH2, NAND, DOWN, TRISTATE, OUTPUT), /* NC */ 215bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ 216bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_A17_PB0, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ 217bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ 218bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_A19_PK7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ 219bf78b271SMarcel Ziswiler 220bf78b271SMarcel Ziswiler DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, NORMAL, NORMAL, OUTPUT), 221bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, OUTPUT), 222bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT), 223bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT), 224bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT), 225bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, OUTPUT), 226bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, OUTPUT), 227bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, OUTPUT), 228bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, OUTPUT), 229bf78b271SMarcel Ziswiler 230bf78b271SMarcel Ziswiler DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), 231bf78b271SMarcel Ziswiler 232bf78b271SMarcel Ziswiler /* multiplexed VI_D2, VI_D3, VI_D4, VI_D5, VI_D6, VI_D7, VI_D8 and VI_D9 233bf78b271SMarcel Ziswiler */ 234bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW0_PR0, RSVD2, NORMAL, TRISTATE, INPUT), 235bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW1_PR1, RSVD2, NORMAL, TRISTATE, INPUT), 236bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW2_PR2, RSVD2, NORMAL, TRISTATE, INPUT), 237bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW3_PR3, RSVD2, NORMAL, TRISTATE, INPUT), 238bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW4_PR4, RSVD3, NORMAL, TRISTATE, INPUT), 239bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT), 240bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT), 241bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, TRISTATE, INPUT), 242bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, TRISTATE, INPUT), 243bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, TRISTATE, INPUT), 244bf78b271SMarcel Ziswiler 245bf78b271SMarcel Ziswiler /* GPIOs */ 246bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW10_PS2, SDMMC2, NORMAL, NORMAL, INPUT), 247bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW11_PS3, SDMMC2, NORMAL, NORMAL, INPUT), 248bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW12_PS4, SDMMC2, NORMAL, NORMAL, INPUT), 249bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW13_PS5, SDMMC2, NORMAL, NORMAL, INPUT), 250bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW14_PS6, SDMMC2, NORMAL, NORMAL, INPUT), 251bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW15_PS7, SDMMC2, NORMAL, NORMAL, INPUT), 252bf78b271SMarcel Ziswiler 253bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, NORMAL, INPUT), 254bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, INPUT), 255bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_COL2_PQ2, KBC, NORMAL, NORMAL, INPUT), 256bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT), 257bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_COL4_PQ4, KBC, NORMAL, NORMAL, INPUT), 258bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, NORMAL, INPUT), 259bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_COL6_PQ6, KBC, NORMAL, NORMAL, INPUT), 260bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, NORMAL, INPUT), 261bf78b271SMarcel Ziswiler 262bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PV0, RSVD1, NORMAL, NORMAL, INPUT), 263bf78b271SMarcel Ziswiler 264bf78b271SMarcel Ziswiler DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, DOWN, TRISTATE, OUTPUT), /* NC */ 265bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT), 266bf78b271SMarcel Ziswiler /* multiplexed KB_COL0 */ 267bf78b271SMarcel Ziswiler DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), 268bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), 269bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), 270bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), 271bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), 272bf78b271SMarcel Ziswiler DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, OUTPUT), 273bf78b271SMarcel Ziswiler DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), 274bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), 275bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), 276bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, TRISTATE, OUTPUT), 277bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, OUTPUT), 278bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, TRISTATE, OUTPUT), 279bf78b271SMarcel Ziswiler DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, TRISTATE, OUTPUT), 280bf78b271SMarcel Ziswiler 281bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT), 282bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), 283bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), 284bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), 285bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), 286bf78b271SMarcel Ziswiler 287*b4f90104SMarcel Ziswiler DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, INPUT), 288*b4f90104SMarcel Ziswiler DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, RSVD2, NORMAL, NORMAL, INPUT), 289*b4f90104SMarcel Ziswiler DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, RSVD2, NORMAL, NORMAL, INPUT), 290bf78b271SMarcel Ziswiler 291*b4f90104SMarcel Ziswiler DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, RSVD2, DOWN, TRISTATE, OUTPUT), /* NC */ 292*b4f90104SMarcel Ziswiler DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT), /* NC */ 293*b4f90104SMarcel Ziswiler DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT), /* NC */ 294*b4f90104SMarcel Ziswiler 295bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), 296bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), 297bf78b271SMarcel Ziswiler DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), 298*b4f90104SMarcel Ziswiler DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), 299*b4f90104SMarcel Ziswiler 300bf78b271SMarcel Ziswiler DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), 301bf78b271SMarcel Ziswiler DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, NORMAL, INPUT), 302bf78b271SMarcel Ziswiler 303bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */ 304bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD12_PH4, NAND, DOWN, TRISTATE, OUTPUT), /* NC */ 305bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD14_PH6, NAND, DOWN, TRISTATE, OUTPUT), /* NC */ 306bf78b271SMarcel Ziswiler 307bf78b271SMarcel Ziswiler DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT), 308bf78b271SMarcel Ziswiler DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, NORMAL, INPUT), 309bf78b271SMarcel Ziswiler }; 310bf78b271SMarcel Ziswiler 311bf78b271SMarcel Ziswiler static struct pmux_pingrp_config unused_pins_lowpower[] = { 312bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, DOWN, TRISTATE, OUTPUT), 313bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, DOWN, TRISTATE, OUTPUT), 314bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_CLK_PK1, NAND, DOWN, TRISTATE, OUTPUT), 315bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, DOWN, TRISTATE, OUTPUT), 316bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, DOWN, TRISTATE, OUTPUT), 317bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD0_PG0, NAND, DOWN, TRISTATE, OUTPUT), 318bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD1_PG1, NAND, DOWN, TRISTATE, OUTPUT), 319bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD2_PG2, NAND, DOWN, TRISTATE, OUTPUT), 320bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD3_PG3, NAND, DOWN, TRISTATE, OUTPUT), 321bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD4_PG4, NAND, DOWN, TRISTATE, OUTPUT), 322bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD5_PG5, NAND, DOWN, TRISTATE, OUTPUT), 323bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD6_PG6, NAND, DOWN, TRISTATE, OUTPUT), 324bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD7_PG7, NAND, DOWN, TRISTATE, OUTPUT), 325bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, DOWN, TRISTATE, OUTPUT), 326bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD11_PH3, NAND, DOWN, TRISTATE, OUTPUT), 327bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_AD13_PH5, NAND, DOWN, TRISTATE, OUTPUT), 328bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, DOWN, TRISTATE, OUTPUT), 329bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, NORMAL, INPUT), 330bf78b271SMarcel Ziswiler DEFAULT_PINMUX(GMI_DQS_PI2, NAND, DOWN, TRISTATE, OUTPUT), 331bf78b271SMarcel Ziswiler }; 332bf78b271SMarcel Ziswiler 333bf78b271SMarcel Ziswiler static struct pmux_drvgrp_config apalis_t30_padctrl[] = { 334bf78b271SMarcel Ziswiler /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ 335bf78b271SMarcel Ziswiler DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ 336bf78b271SMarcel Ziswiler SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), 337bf78b271SMarcel Ziswiler }; 338bf78b271SMarcel Ziswiler #endif /* _PINMUX_CONFIG_APALIS_T30_H_ */ 339