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/openbmc/linux/arch/parisc/include/asm/
H A Dasmregs.h11 rp: .reg %r2
12 arg3: .reg %r23
13 arg2: .reg %r24
14 arg1: .reg %r25
15 arg0: .reg %r26
16 dp: .reg %r27
17 ret0: .reg %r28
18 ret1: .reg %r29
19 sl: .reg %r29
20 sp: .reg %r30
[all …]
/openbmc/qemu/target/i386/tcg/
H A Dops_sse_header.h.inc20 #define Reg MMXReg
23 #define Reg ZMMReg
34 #define dh_ctype_Reg Reg *
41 DEF_HELPER_4(glue(psrlw, SUFFIX), void, env, Reg, Reg, Reg)
42 DEF_HELPER_4(glue(psraw, SUFFIX), void, env, Reg, Reg, Reg)
43 DEF_HELPER_4(glue(psllw, SUFFIX), void, env, Reg, Reg, Reg)
44 DEF_HELPER_4(glue(psrld, SUFFIX), void, env, Reg, Reg, Reg)
45 DEF_HELPER_4(glue(psrad, SUFFIX), void, env, Reg, Reg, Reg)
46 DEF_HELPER_4(glue(pslld, SUFFIX), void, env, Reg, Reg, Reg)
47 DEF_HELPER_4(glue(psrlq, SUFFIX), void, env, Reg, Reg, Reg)
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dasm-eva.h19 #define kernel_ll(reg, addr) "ll " reg ", " addr "\n" argument
20 #define kernel_sc(reg, addr) "sc " reg ", " addr "\n" argument
21 #define kernel_lw(reg, addr) "lw " reg ", " addr "\n" argument
22 #define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n" argument
23 #define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n" argument
24 #define kernel_lh(reg, addr) "lh " reg ", " addr "\n" argument
25 #define kernel_lb(reg, addr) "lb " reg ", " addr "\n" argument
26 #define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n" argument
27 #define kernel_sw(reg, addr) "sw " reg ", " addr "\n" argument
28 #define kernel_swl(reg, addr) "swl " reg ", " addr "\n" argument
[all …]
/openbmc/linux/drivers/net/ethernet/mscc/
H A Dvsc7514_regs.c72 REG(ANA_ADVLEARN, 0x009000),
73 REG(ANA_VLANMASK, 0x009004),
74 REG(ANA_PORT_B_DOMAIN, 0x009008),
75 REG(ANA_ANAGEFIL, 0x00900c),
76 REG(ANA_ANEVENTS, 0x009010),
77 REG(ANA_STORMLIMIT_BURST, 0x009014),
78 REG(ANA_STORMLIMIT_CFG, 0x009018),
79 REG(ANA_ISOLATED_PORTS, 0x009028),
80 REG(ANA_COMMUNITY_PORTS, 0x00902c),
81 REG(ANA_AUTOAGE, 0x009030),
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.c28 u32 reg; in analogix_dp_enable_video_mute() local
31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
32 reg |= HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
36 reg &= ~HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
43 u32 reg; in analogix_dp_stop_video() local
45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
46 reg &= ~VIDEO_EN; in analogix_dp_stop_video()
[all …]
/openbmc/linux/tools/testing/selftests/powerpc/include/
H A Dvmx_asm.h9 #define PUSH_VMX(pos,reg) \ argument
10 li reg,pos; \
11 stvx v20,reg,%r1; \
12 addi reg,reg,16; \
13 stvx v21,reg,%r1; \
14 addi reg,reg,16; \
15 stvx v22,reg,%r1; \
16 addi reg,reg,16; \
17 stvx v23,reg,%r1; \
18 addi reg,reg,16; \
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dreg_helper.h36 * REG ==> macro to location of register offset
37 * eg. aud110->regs->reg
40 dm_read_reg(CTX, REG(reg_name))
43 dm_write_reg(CTX, REG(reg_name), value)
56 REG(reg_name), \
67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ argument
68 REG_SET_N(reg, 2, init_value, \
69 FN(reg, f1), v1,\
70 FN(reg, f2), v2)
72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
[all …]
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_dp_lowlevel.c22 unsigned int reg; in exynos_dp_enable_video_input() local
24 reg = readl(&dp_regs->video_ctl1); in exynos_dp_enable_video_input()
25 reg &= ~VIDEO_EN_MASK; in exynos_dp_enable_video_input()
29 reg |= VIDEO_EN_MASK; in exynos_dp_enable_video_input()
31 writel(reg, &dp_regs->video_ctl1); in exynos_dp_enable_video_input()
39 unsigned int reg; in exynos_dp_enable_video_bist() local
41 reg = readl(&dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
42 reg &= ~VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
46 reg |= VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
48 writel(reg, &dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
[all …]
H A Dexynos_mipi_dsi_lowlevel.c20 unsigned int reg; in exynos_mipi_dsi_func_reset() local
25 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
27 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_func_reset()
29 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
34 unsigned int reg = 0; in exynos_mipi_dsi_sw_reset() local
39 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
41 reg |= DSIM_SWRST; in exynos_mipi_dsi_sw_reset()
42 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_sw_reset()
44 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
51 unsigned int reg = readl(&mipi_dsim->intsrc); in exynos_mipi_dsi_sw_release() local
[all …]
/openbmc/linux/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-hw-s5p.c19 unsigned long reg; in s5p_jpeg_reset() local
22 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
24 while (reg != 0) { in s5p_jpeg_reset()
26 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
37 unsigned long reg, m; in s5p_jpeg_input_raw_mode() local
45 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
46 reg &= ~S5P_MOD_SEL_MASK; in s5p_jpeg_input_raw_mode()
47 reg |= m; in s5p_jpeg_input_raw_mode()
48 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
53 unsigned long reg, m; in s5p_jpeg_proc_mode() local
[all …]
H A Djpeg-hw-exynos4.c18 unsigned int reg; in exynos4_jpeg_sw_reset() local
20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
21 writel(reg & ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE), in exynos4_jpeg_sw_reset()
24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
34 unsigned int reg; in exynos4_jpeg_set_enc_dec_mode() local
36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
39 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
43 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
[all …]
H A Djpeg-hw-exynos3250.c20 u32 reg = 1; in exynos3250_jpeg_reset() local
25 while (reg != 0 && --count > 0) { in exynos3250_jpeg_reset()
28 reg = readl(regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset()
31 reg = 0; in exynos3250_jpeg_reset()
34 while (reg != 1 && --count > 0) { in exynos3250_jpeg_reset()
38 reg = readl(regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
62 u32 reg; in exynos3250_jpeg_clk_set() local
64 reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; in exynos3250_jpeg_clk_set()
66 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_clk_set()
71 u32 reg; in exynos3250_jpeg_input_raw_fmt() local
[all …]
/openbmc/linux/drivers/media/cec/platform/s5p/
H A Dexynos_hdmi_cecctrl.c26 unsigned int reg; in s5p_cec_set_divider() local
30 if (regmap_read(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, &reg)) { in s5p_cec_set_divider()
35 reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16); in s5p_cec_set_divider()
37 if (regmap_write(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, reg)) { in s5p_cec_set_divider()
44 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_3); in s5p_cec_set_divider()
45 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_2); in s5p_cec_set_divider()
46 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_1); in s5p_cec_set_divider()
47 writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0); in s5p_cec_set_divider()
52 u8 reg; in s5p_cec_enable_rx() local
54 reg = readb(cec->reg + S5P_CEC_RX_CTRL); in s5p_cec_enable_rx()
[all …]
/openbmc/linux/drivers/accel/ivpu/
H A Divpu_hw_reg_io.h18 #define REGB_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regb, (reg), #reg, __func__) argument
19 #define REGB_RD32_SILENT(reg) readl(vdev->regb + (reg)) argument
20 #define REGB_RD64(reg) ivpu_hw_reg_rd64(vdev, vdev->regb, (reg), #reg, __func__) argument
21 #define REGB_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regb, (reg), (val), #reg, __func__) argument
22 #define REGB_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regb, (reg), (val), #reg, __func__) argument
24 #define REGV_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regv, (reg), #reg, __func__) argument
25 #define REGV_RD32_SILENT(reg) readl(vdev->regv + (reg)) argument
26 #define REGV_RD64(reg) ivpu_hw_reg_rd64(vdev, vdev->regv, (reg), #reg, __func__) argument
27 #define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__) argument
28 #define REGV_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regv, (reg), (val), #reg, __func__) argument
[all …]
/openbmc/qemu/gdb-xml/
H A Dmicroblaze-core.xml10 <reg name="r0" bitsize="32" regnum="0"/>
11 <reg name="r1" bitsize="32" type="data_ptr"/>
12 <reg name="r2" bitsize="32"/>
13 <reg name="r3" bitsize="32"/>
14 <reg name="r4" bitsize="32"/>
15 <reg name="r5" bitsize="32"/>
16 <reg name="r6" bitsize="32"/>
17 <reg name="r7" bitsize="32"/>
18 <reg name="r8" bitsize="32"/>
19 <reg name="r9" bitsize="32"/>
[all …]
/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_dbg.c107 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla27xx_dump_mpi_ram() local
118 if (qla_pci_disconnected(vha, reg)) in qla27xx_dump_mpi_ram()
125 wrt_reg_word(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM); in qla27xx_dump_mpi_ram()
126 wrt_reg_word(&reg->mailbox1, LSW(addr)); in qla27xx_dump_mpi_ram()
127 wrt_reg_word(&reg->mailbox8, MSW(addr)); in qla27xx_dump_mpi_ram()
129 wrt_reg_word(&reg->mailbox2, MSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram()
130 wrt_reg_word(&reg->mailbox3, LSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram()
131 wrt_reg_word(&reg->mailbox6, MSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
132 wrt_reg_word(&reg->mailbox7, LSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
134 wrt_reg_word(&reg->mailbox4, MSW(dwords)); in qla27xx_dump_mpi_ram()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h36 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) argument
37 #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \ argument
38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ argument
42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
43 WREG32(reg, value))
45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \ argument
47 amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \
48 RREG32(reg))
50 #define WREG32_FIELD15(ip, idx, reg, field, val) \ argument
[all …]
/openbmc/linux/arch/riscv/include/asm/
H A Dgdb_xml.h26 "<reg name=\""DBG_REG_ZERO"\" bitsize=\"64\" type=\"int\" regnum=\"0\"/>"
27 "<reg name=\""DBG_REG_RA"\" bitsize=\"64\" type=\"code_ptr\"/>"
28 "<reg name=\""DBG_REG_SP"\" bitsize=\"64\" type=\"data_ptr\"/>"
29 "<reg name=\""DBG_REG_GP"\" bitsize=\"64\" type=\"data_ptr\"/>"
30 "<reg name=\""DBG_REG_TP"\" bitsize=\"64\" type=\"data_ptr\"/>"
31 "<reg name=\""DBG_REG_T0"\" bitsize=\"64\" type=\"int\"/>"
32 "<reg name=\""DBG_REG_T1"\" bitsize=\"64\" type=\"int\"/>"
33 "<reg name=\""DBG_REG_T2"\" bitsize=\"64\" type=\"int\"/>"
34 "<reg name=\""DBG_REG_FP"\" bitsize=\"64\" type=\"data_ptr\"/>"
35 "<reg name=\""DBG_REG_S1"\" bitsize=\"64\" type=\"int\"/>"
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c58 printf("\n write reg 0x%08x = 0x%08x", addr, val); in dfs_reg_write()
70 u32 reg; in wait_refresh_op_complete() local
74 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in wait_refresh_op_complete()
76 } while (reg); /* Wait for '0' */ in wait_refresh_op_complete()
116 u32 reg, freq_par, tmp; in ddr3_dfs_high_2_low() local
132 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
134 reg |= (1 << REG_DFS_DLLNEXTSTATE_OFFS); in ddr3_dfs_high_2_low()
135 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
141 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_high_2_low()
143 reg &= ~(1 << REG_METAL_MASK_RETRY_OFFS); in ddr3_dfs_high_2_low()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-38x-controlcenterdc.dts59 reg = <0x00000000 0x10000000>; /* 256 MB */
81 reg = <0x21>;
88 reg = <0x22>;
94 reg = <0x23>;
100 reg = <0x24>;
106 reg = <0x25>;
112 reg = <0x26>;
123 reg = <0x29>;
130 reg = <0x2d>;
132 reg = <0>;
[all …]
/openbmc/linux/drivers/video/fbdev/riva/
H A Dnvreg.h44 #define DEVICE_ACCESS(device,reg) \ argument
45 nvCONTROL[(NV_##device##_##reg)/4]
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
48 #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) argument
49 #define DEVICE_PRINT(device,reg) \ argument
50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
57 #define PDAC_Read(reg) DEVICE_READ(PDAC,reg) argument
58 #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) argument
63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) argument
[all …]
/openbmc/linux/tools/perf/arch/csky/util/
H A Dunwind-libdw.c16 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
23 dwarf_regs[0] = REG(A0); in libdw__arch_set_initial_registers()
24 dwarf_regs[1] = REG(A1); in libdw__arch_set_initial_registers()
25 dwarf_regs[2] = REG(A2); in libdw__arch_set_initial_registers()
26 dwarf_regs[3] = REG(A3); in libdw__arch_set_initial_registers()
27 dwarf_regs[4] = REG(REGS0); in libdw__arch_set_initial_registers()
28 dwarf_regs[5] = REG(REGS1); in libdw__arch_set_initial_registers()
29 dwarf_regs[6] = REG(REGS2); in libdw__arch_set_initial_registers()
30 dwarf_regs[7] = REG(REGS3); in libdw__arch_set_initial_registers()
31 dwarf_regs[8] = REG(REGS4); in libdw__arch_set_initial_registers()
[all …]
/openbmc/linux/drivers/media/platform/nxp/imx-jpeg/
H A Dmxc-jpeg-hw.c18 dev_dbg(dev, "Wrapper reg %s = 0x%x\n", reg_name, val);\
35 void print_cast_status(struct device *dev, void __iomem *reg, in print_cast_status() argument
39 print_wrapper_reg(dev, reg, CAST_STATUS0); in print_cast_status()
40 print_wrapper_reg(dev, reg, CAST_STATUS1); in print_cast_status()
41 print_wrapper_reg(dev, reg, CAST_STATUS2); in print_cast_status()
42 print_wrapper_reg(dev, reg, CAST_STATUS3); in print_cast_status()
43 print_wrapper_reg(dev, reg, CAST_STATUS4); in print_cast_status()
44 print_wrapper_reg(dev, reg, CAST_STATUS5); in print_cast_status()
45 print_wrapper_reg(dev, reg, CAST_STATUS6); in print_cast_status()
46 print_wrapper_reg(dev, reg, CAST_STATUS7); in print_cast_status()
[all …]
/openbmc/qemu/include/hw/
H A Dregisterfields.h21 #define REG32(reg, addr) \ argument
22 enum { A_ ## reg = (addr) }; \
23 enum { R_ ## reg = (addr) / 4 };
25 #define REG8(reg, addr) \ argument
26 enum { A_ ## reg = (addr) }; \
27 enum { R_ ## reg = (addr) };
29 #define REG16(reg, addr) \ argument
30 enum { A_ ## reg = (addr) }; \
31 enum { R_ ## reg = (addr) / 2 };
33 #define REG64(reg, addr) \ argument
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3701.dtsi21 reg = <0>;
29 reg = <1>;
47 reg = <0>;
55 reg = <1>;
73 reg = <0>;
81 reg = <1>;
99 reg = <0>;
107 reg = <1>;
125 reg = <0>;
133 reg = <1>;
[all …]

12345678910>>...329