20 	unsigned int reg;  in exynos_mipi_dsi_func_reset()  local
25 	reg = readl(&mipi_dsim->swrst);  in exynos_mipi_dsi_func_reset()
27 	reg |= DSIM_FUNCRST;  in exynos_mipi_dsi_func_reset()
29 	writel(reg, &mipi_dsim->swrst);  in exynos_mipi_dsi_func_reset()
34 	unsigned int reg = 0;  in exynos_mipi_dsi_sw_reset()  local
39 	reg = readl(&mipi_dsim->swrst);  in exynos_mipi_dsi_sw_reset()
41 	reg |= DSIM_SWRST;  in exynos_mipi_dsi_sw_reset()
42 	reg |= DSIM_FUNCRST;  in exynos_mipi_dsi_sw_reset()
44 	writel(reg, &mipi_dsim->swrst);  in exynos_mipi_dsi_sw_reset()
51 	unsigned int reg = readl(&mipi_dsim->intsrc);  in exynos_mipi_dsi_sw_release()  local
53 	reg |= INTSRC_SWRST_RELEASE;  in exynos_mipi_dsi_sw_release()
55 	writel(reg, &mipi_dsim->intsrc);  in exynos_mipi_dsi_sw_release()
63 	unsigned int reg = readl(&mipi_dsim->intmsk);  in exynos_mipi_dsi_set_interrupt_mask()  local
66 		reg |= mode;  in exynos_mipi_dsi_set_interrupt_mask()
68 		reg &= ~mode;  in exynos_mipi_dsi_set_interrupt_mask()
70 	writel(reg, &mipi_dsim->intmsk);  in exynos_mipi_dsi_set_interrupt_mask()
76 	unsigned int reg;  in exynos_mipi_dsi_init_fifo_pointer()  local
80 	reg = readl(&mipi_dsim->fifoctrl);  in exynos_mipi_dsi_init_fifo_pointer()
82 	writel(reg & ~(cfg), &mipi_dsim->fifoctrl);  in exynos_mipi_dsi_init_fifo_pointer()
84 	reg |= cfg;  in exynos_mipi_dsi_init_fifo_pointer()
86 	writel(reg, &mipi_dsim->fifoctrl);  in exynos_mipi_dsi_init_fifo_pointer()
104 	unsigned int reg;  in exynos_mipi_dsi_set_main_disp_resol()  local
109 	reg = (readl(&mipi_dsim->mdresol)) & ~(DSIM_MAIN_STAND_BY);  in exynos_mipi_dsi_set_main_disp_resol()
110 	writel(reg, &mipi_dsim->mdresol);  in exynos_mipi_dsi_set_main_disp_resol()
113 	reg &= ~(DSIM_MAIN_VRESOL(0x7ff) | DSIM_MAIN_HRESOL(0x7ff));  in exynos_mipi_dsi_set_main_disp_resol()
114 	reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol);  in exynos_mipi_dsi_set_main_disp_resol()
116 	reg |= DSIM_MAIN_STAND_BY;  in exynos_mipi_dsi_set_main_disp_resol()
117 	writel(reg, &mipi_dsim->mdresol);  in exynos_mipi_dsi_set_main_disp_resol()
123 	unsigned int reg;  in exynos_mipi_dsi_set_main_disp_vporch()  local
127 	reg = (readl(&mipi_dsim->mvporch)) &  in exynos_mipi_dsi_set_main_disp_vporch()
131 	reg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) |  in exynos_mipi_dsi_set_main_disp_vporch()
135 	writel(reg, &mipi_dsim->mvporch);  in exynos_mipi_dsi_set_main_disp_vporch()
141 	unsigned int reg;  in exynos_mipi_dsi_set_main_disp_hporch()  local
145 	reg = (readl(&mipi_dsim->mhporch)) &  in exynos_mipi_dsi_set_main_disp_hporch()
148 	reg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT);  in exynos_mipi_dsi_set_main_disp_hporch()
150 	writel(reg, &mipi_dsim->mhporch);  in exynos_mipi_dsi_set_main_disp_hporch()
156 	unsigned int reg;  in exynos_mipi_dsi_set_main_disp_sync_area()  local
160 	reg = (readl(&mipi_dsim->msync)) &  in exynos_mipi_dsi_set_main_disp_sync_area()
163 	reg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) |  in exynos_mipi_dsi_set_main_disp_sync_area()
166 	writel(reg, &mipi_dsim->msync);  in exynos_mipi_dsi_set_main_disp_sync_area()
172 	unsigned int reg;  in exynos_mipi_dsi_set_sub_disp_resol()  local
176 	reg = (readl(&mipi_dsim->sdresol)) &  in exynos_mipi_dsi_set_sub_disp_resol()
179 	writel(reg, &mipi_dsim->sdresol);  in exynos_mipi_dsi_set_sub_disp_resol()
181 	reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);  in exynos_mipi_dsi_set_sub_disp_resol()
182 	reg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) |  in exynos_mipi_dsi_set_sub_disp_resol()
184 	writel(reg, &mipi_dsim->sdresol);  in exynos_mipi_dsi_set_sub_disp_resol()
187 	reg |= (1 << DSIM_SUB_STANDY_SHIFT);  in exynos_mipi_dsi_set_sub_disp_resol()
188 	writel(reg, &mipi_dsim->sdresol);  in exynos_mipi_dsi_set_sub_disp_resol()
219 	u32 reg = (readl(&mipi_dsim->config)) &  in exynos_mipi_dsi_display_config()  local
225 		reg |= (1 << DSIM_VIDEO_MODE_SHIFT);  in exynos_mipi_dsi_display_config()
227 		reg &= ~(1 << DSIM_VIDEO_MODE_SHIFT);  in exynos_mipi_dsi_display_config()
234 	reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << DSIM_BURST_MODE_SHIFT  in exynos_mipi_dsi_display_config()
238 	writel(reg, &mipi_dsim->config);  in exynos_mipi_dsi_display_config()
244 	unsigned int reg;  in exynos_mipi_dsi_enable_lane()  local
248 	reg = readl(&mipi_dsim->config);  in exynos_mipi_dsi_enable_lane()
251 		reg |= DSIM_LANE_ENx(lane);  in exynos_mipi_dsi_enable_lane()
253 		reg &= ~DSIM_LANE_ENx(lane);  in exynos_mipi_dsi_enable_lane()
255 	writel(reg, &mipi_dsim->config);  in exynos_mipi_dsi_enable_lane()
276 	unsigned int reg = readl(&mipi_dsim->phyacchr);  in exynos_mipi_dsi_enable_afc()  local
278 	reg = 0;  in exynos_mipi_dsi_enable_afc()
281 		reg |= DSIM_AFC_EN;  in exynos_mipi_dsi_enable_afc()
282 		reg &= ~(0x7 << DSIM_AFC_CTL_SHIFT);  in exynos_mipi_dsi_enable_afc()
283 		reg |= DSIM_AFC_CTL(afc_code);  in exynos_mipi_dsi_enable_afc()
285 		reg &= ~DSIM_AFC_EN;  in exynos_mipi_dsi_enable_afc()
287 	writel(reg, &mipi_dsim->phyacchr);  in exynos_mipi_dsi_enable_afc()
295 	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &  in exynos_mipi_dsi_enable_pll_bypass()  local
298 	reg |= enable << DSIM_PLL_BYPASS_SHIFT;  in exynos_mipi_dsi_enable_pll_bypass()
300 	writel(reg, &mipi_dsim->clkctrl);  in exynos_mipi_dsi_enable_pll_bypass()
308 	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &  in exynos_mipi_dsi_pll_freq_band()  local
311 	reg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT);  in exynos_mipi_dsi_pll_freq_band()
313 	writel(reg, &mipi_dsim->pllctrl);  in exynos_mipi_dsi_pll_freq_band()
322 	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &  in exynos_mipi_dsi_pll_freq()  local
325 	reg |= ((pre_divider & 0x3f) << DSIM_PREDIV_SHIFT) |  in exynos_mipi_dsi_pll_freq()
329 	writel(reg, &mipi_dsim->pllctrl);  in exynos_mipi_dsi_pll_freq()
346 	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &  in exynos_mipi_dsi_enable_pll()  local
349 	reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT);  in exynos_mipi_dsi_enable_pll()
351 	writel(reg, &mipi_dsim->pllctrl);  in exynos_mipi_dsi_enable_pll()
359 	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &  in exynos_mipi_dsi_set_byte_clock_src()  local
362 	reg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT;  in exynos_mipi_dsi_set_byte_clock_src()
364 	writel(reg, &mipi_dsim->clkctrl);  in exynos_mipi_dsi_set_byte_clock_src()
372 	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &  in exynos_mipi_dsi_enable_byte_clock()  local
375 	reg |= enable << DSIM_BYTE_CLKEN_SHIFT;  in exynos_mipi_dsi_enable_byte_clock()
377 	writel(reg, &mipi_dsim->clkctrl);  in exynos_mipi_dsi_enable_byte_clock()
385 	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &  in exynos_mipi_dsi_set_esc_clk_prs()  local
388 	reg |= enable << DSIM_ESC_CLKEN_SHIFT;  in exynos_mipi_dsi_set_esc_clk_prs()
390 		reg |= prs_val;  in exynos_mipi_dsi_set_esc_clk_prs()
392 	writel(reg, &mipi_dsim->clkctrl);  in exynos_mipi_dsi_set_esc_clk_prs()
400 	unsigned int reg = readl(&mipi_dsim->clkctrl);  in exynos_mipi_dsi_enable_esc_clk_on_lane()  local
403 		reg |= DSIM_LANE_ESC_CLKEN(lane_sel);  in exynos_mipi_dsi_enable_esc_clk_on_lane()
405 		reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel);  in exynos_mipi_dsi_enable_esc_clk_on_lane()
407 	writel(reg, &mipi_dsim->clkctrl);  in exynos_mipi_dsi_enable_esc_clk_on_lane()
415 	unsigned int reg = (readl(&mipi_dsim->escmode)) &  in exynos_mipi_dsi_force_dphy_stop_state()  local
418 	reg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT);  in exynos_mipi_dsi_force_dphy_stop_state()
420 	writel(reg, &mipi_dsim->escmode);  in exynos_mipi_dsi_force_dphy_stop_state()
427 	unsigned int reg = readl(&mipi_dsim->status);  in exynos_mipi_dsi_is_lane_state()  local
435 	if ((reg & DSIM_STOP_STATE_DAT(0xf)) &&  in exynos_mipi_dsi_is_lane_state()
436 			((reg & DSIM_STOP_STATE_CLK) ||  in exynos_mipi_dsi_is_lane_state()
437 			 (reg & DSIM_TX_READY_HS_CLK)))  in exynos_mipi_dsi_is_lane_state()
448 	unsigned int reg = (readl(&mipi_dsim->escmode)) &  in exynos_mipi_dsi_set_stop_state_counter()  local
451 	reg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT);  in exynos_mipi_dsi_set_stop_state_counter()
453 	writel(reg, &mipi_dsim->escmode);  in exynos_mipi_dsi_set_stop_state_counter()
461 	unsigned int reg = (readl(&mipi_dsim->timeout)) &  in exynos_mipi_dsi_set_bta_timeout()  local
464 	reg |= (timeout << DSIM_BTA_TOUT_SHIFT);  in exynos_mipi_dsi_set_bta_timeout()
466 	writel(reg, &mipi_dsim->timeout);  in exynos_mipi_dsi_set_bta_timeout()
474 	unsigned int reg = (readl(&mipi_dsim->timeout)) &  in exynos_mipi_dsi_set_lpdr_timeout()  local
477 	reg |= (timeout << DSIM_LPDR_TOUT_SHIFT);  in exynos_mipi_dsi_set_lpdr_timeout()
479 	writel(reg, &mipi_dsim->timeout);  in exynos_mipi_dsi_set_lpdr_timeout()
487 	unsigned int reg = readl(&mipi_dsim->escmode);  in exynos_mipi_dsi_set_cpu_transfer_mode()  local
489 	reg &= ~DSIM_CMD_LPDT_LP;  in exynos_mipi_dsi_set_cpu_transfer_mode()
492 		reg |= DSIM_CMD_LPDT_LP;  in exynos_mipi_dsi_set_cpu_transfer_mode()
494 	writel(reg, &mipi_dsim->escmode);  in exynos_mipi_dsi_set_cpu_transfer_mode()
502 	unsigned int reg = readl(&mipi_dsim->escmode);  in exynos_mipi_dsi_set_lcdc_transfer_mode()  local
504 	reg &= ~DSIM_TX_LPDT_LP;  in exynos_mipi_dsi_set_lcdc_transfer_mode()
507 		reg |= DSIM_TX_LPDT_LP;  in exynos_mipi_dsi_set_lcdc_transfer_mode()
509 	writel(reg, &mipi_dsim->escmode);  in exynos_mipi_dsi_set_lcdc_transfer_mode()
517 	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &  in exynos_mipi_dsi_enable_hs_clock()  local
520 	reg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT;  in exynos_mipi_dsi_enable_hs_clock()
522 	writel(reg, &mipi_dsim->clkctrl);  in exynos_mipi_dsi_enable_hs_clock()
530 	unsigned int reg = readl(&mipi_dsim->phyacchr1);  in exynos_mipi_dsi_dp_dn_swap()  local
532 	reg &= ~(0x3 << DSIM_DPDN_SWAP_DATA_SHIFT);  in exynos_mipi_dsi_dp_dn_swap()
533 	reg |= (swap_en & 0x3) << DSIM_DPDN_SWAP_DATA_SHIFT;  in exynos_mipi_dsi_dp_dn_swap()
535 	writel(reg, &mipi_dsim->phyacchr1);  in exynos_mipi_dsi_dp_dn_swap()
543 	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &  in exynos_mipi_dsi_hs_zero_ctrl()  local
546 	reg |= ((hs_zero & 0xf) << DSIM_ZEROCTRL_SHIFT);  in exynos_mipi_dsi_hs_zero_ctrl()
548 	writel(reg, &mipi_dsim->pllctrl);  in exynos_mipi_dsi_hs_zero_ctrl()
555 	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &  in exynos_mipi_dsi_prep_ctrl()  local
558 	reg |= ((prep & 0x7) << DSIM_PRECTRL_SHIFT);  in exynos_mipi_dsi_prep_ctrl()
560 	writel(reg, &mipi_dsim->pllctrl);  in exynos_mipi_dsi_prep_ctrl()
567 	unsigned int reg = readl(&mipi_dsim->intsrc);  in exynos_mipi_dsi_clear_interrupt()  local
569 	reg |= INTSRC_PLL_STABLE;  in exynos_mipi_dsi_clear_interrupt()
571 	writel(reg, &mipi_dsim->intsrc);  in exynos_mipi_dsi_clear_interrupt()
584 	unsigned int reg;  in exynos_mipi_dsi_is_pll_stable()  local
588 	reg = readl(&mipi_dsim->status);  in exynos_mipi_dsi_is_pll_stable()
590 	return reg & DSIM_PLL_STABLE ? 1 : 0;  in exynos_mipi_dsi_is_pll_stable()
606 	unsigned int reg = (DSIM_PKTHDR_DAT1(data1) | DSIM_PKTHDR_DAT0(data0) |  in exynos_mipi_dsi_wr_tx_header()  local
609 	writel(reg, &mipi_dsim->pkthdr);  in exynos_mipi_dsi_wr_tx_header()
617 	unsigned int reg = readl(&mipi_dsim->intsrc);  in _exynos_mipi_dsi_get_frame_done_status()  local
619 	return (reg & INTSRC_FRAME_DONE) ? 1 : 0;  in _exynos_mipi_dsi_get_frame_done_status()
626 	unsigned int reg = readl(&mipi_dsim->intsrc);  in _exynos_mipi_dsi_clear_frame_done()  local
628 	writel(reg | INTSRC_FRAME_DONE, &mipi_dsim->intsrc);  in _exynos_mipi_dsi_clear_frame_done()