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Searched +full:pll1 +full:- +full:refclk (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,mpfs-ccc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Conor Dooley <conor.dooley@microchip.com>
16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
20 const: microchip,mpfs-ccc
24 - description: PLL0's control registers
25 - description: PLL1's control registers
26 - description: DLL0's control registers
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c38 struct nvkm_subdev *subdev = &init->subdev; in nv04_devinit_meminit()
39 struct nvkm_device *device = subdev->device; in nv04_devinit_meminit()
115 int shift = -4; in powerctrl_1_shift()
137 shift = -4; in powerctrl_1_shift()
146 struct nvkm_device *device = init->subdev.device; in setPLL_single()
147 int chip_version = device->bios->version.chip; in setPLL_single()
150 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_single()
164 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) in setPLL_single()
165 /* upclock -- write new post divider first */ in setPLL_single()
166 nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff)); in setPLL_single()
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
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/openbmc/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c4 * Copyright 2007-2009 Stuart Bennett
92 if (drm->client.device.info.chipset == 0x11) { in NVSetOwner()
103 if (drm->client.device.info.chipset == 0x11) { /* set me harder */ in NVSetOwner()
132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
141 pllvals->N2 = pllvals->M2 = 1; in nouveau_hw_decode_pll()
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
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/openbmc/linux/drivers/phy/ti/
H A Dphy-j721e-wiz.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
13 #include <linux/clk-provider.h>
25 #include <linux/reset-controller.h>
125 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
126 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
127 [TI_WIZ_REFCLK_DIG] = "refclk-dig",
128 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk",
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/openbmc/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
69 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
77 clrsetbits_le32(&mxc_ccm->cscmr1, in set_usboh3_clk()
80 clrsetbits_le32(&mxc_ccm->cscdr1, in set_usboh3_clk()
91 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usboh3_clk()
107 return -EINVAL; in enable_i2c_clk()
111 setbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
113 clrbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
120 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL); in set_usb_phy_clk()
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/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
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H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
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/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <clk-uclass.h>
15 #include <dt-bindings/clock/stm32mp1-clks.h>
16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
401 u8 refclk[REFCLK_SIZE]; member
477 .refclk[0] = (p1), \
478 .refclk[1] = (p2), \
479 .refclk[2] = (p3), \
480 .refclk[3] = (p4), \
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c2 * Copyright © 2006-2016 Intel Corporation
44 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
121 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
122 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
124 shared_dpll[i] = pll->state; in intel_atomic_duplicate_dpll_state()
133 drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); in intel_atomic_get_shared_dpll_state()
135 if (!state->dpll_set) { in intel_atomic_get_shared_dpll_state()
136 state->dpll_set = true; in intel_atomic_get_shared_dpll_state()
138 intel_atomic_duplicate_dpll_state(to_i915(s->dev), in intel_atomic_get_shared_dpll_state()
139 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
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H A Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
148 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
162 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
163 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
165 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
177 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
180 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
181 dev_priv->czclk_freq); in intel_update_czclk()
186 return (crtc_state->active_planes & in is_hdr_mode()
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/openbmc/linux/drivers/phy/broadcom/
H A Dphy-brcm-sata.c1 // SPDX-License-Identifier: GPL-2.0-or-later
196 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
199 switch (priv->version) { in brcm_sata_ctrl_base()
204 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
214 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
215 void __iomem *pcb_base = priv->phy_base; in brcm_sata_phy_wr()
218 if (priv->version == BRCM_SATA_PHY_STB_40NM) in brcm_sata_phy_wr()
219 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); in brcm_sata_phy_wr()
221 pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE); in brcm_sata_phy_wr()
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/openbmc/linux/drivers/clk/renesas/
H A Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
62 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate()
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/openbmc/linux/drivers/clk/
H A Dclk-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
51 val = readl_relaxed(pll->pllcon); in npcm7xx_clk_pll_recalc_rate()
79 return ERR_PTR(-ENOMEM); in npcm7xx_clk_register_pll()
89 pll->pllcon = pllcon; in npcm7xx_clk_register_pll()
90 pll->hw.init = &init; in npcm7xx_clk_register_pll()
92 hw = &pll->hw; in npcm7xx_clk_register_pll()
142 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
143 * this specific clock. Otherwise, set to -1.
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/openbmc/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
28 operating-points-v2 = <&opp_table>;
32 opp_table: opp-table {
33 compatible = "operating-points-v2";
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/openbmc/u-boot/arch/arm/dts/
H A Dda850.dtsi10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <1>;
27 intc: interrupt-controller@fffee000 {
28 compatible = "ti,cp-intc";
29 interrupt-controller;
30 #interrupt-cells = <1>;
31 ti,intc-size = <101>;
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/openbmc/linux/drivers/phy/cadence/
H A Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
464 for (i = 0; i < tbl->num_entries; i++) { in cdns_torrent_get_tbl_vals()
465 if (tbl->entries[i].key == key) in cdns_torrent_get_tbl_vals()
466 return tbl->entries[i].vals; in cdns_torrent_get_tbl_vals()
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