Lines Matching +full:pll1 +full:- +full:refclk
1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
69 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
77 clrsetbits_le32(&mxc_ccm->cscmr1, in set_usboh3_clk()
80 clrsetbits_le32(&mxc_ccm->cscdr1, in set_usboh3_clk()
91 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usboh3_clk()
107 return -EINVAL; in enable_i2c_clk()
111 setbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
113 clrbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
120 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL); in set_usb_phy_clk()
128 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usb_phy1_clk()
142 clrsetbits_le32(&mxc_ccm->CCGR4, in enable_usb_phy1_clk()
151 clrsetbits_le32(&mxc_ccm->CCGR4, in enable_usb_phy2_clk()
163 uint64_t refclk, temp; in decode_pll() local
166 ctrl = readl(&pll->ctrl); in decode_pll()
169 mfn = readl(&pll->hfs_mfn); in decode_pll()
170 mfd = readl(&pll->hfs_mfd); in decode_pll()
171 op = readl(&pll->hfs_op); in decode_pll()
173 mfn = readl(&pll->mfn); in decode_pll()
174 mfd = readl(&pll->mfd); in decode_pll()
175 op = readl(&pll->op); in decode_pll()
190 mfn_abs = -mfn; in decode_pll()
194 refclk = infreq * 2; in decode_pll()
196 refclk *= 2; in decode_pll()
198 do_div(refclk, pdf + 1); in decode_pll()
199 temp = refclk * mfn_abs; in decode_pll()
201 ret = refclk * mfi; in decode_pll()
204 ret -= temp; in decode_pll()
213 * This function returns the Frequency Pre-Multiplier clock.
218 u32 ccr = readl(&mxc_ccm->ccr); in get_fpm()
235 u32 ccsr = readl(&mxc_ccm->ccsr); in get_lp_apm()
256 reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr)); in get_mcu_main_clk()
268 reg = readl(&mxc_ccm->cbcdr); in get_periph_clk()
271 reg = readl(&mxc_ccm->cbcmr); in get_periph_clk()
294 reg = readl(&mxc_ccm->cbcdr); in get_ipg_clk()
307 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) in get_ipg_per_clk()
310 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) in get_ipg_per_clk()
314 podf = readl(&mxc_ccm->cbcdr); in get_ipg_per_clk()
351 reg = readl(&mxc_ccm->cscmr1); in get_uart_clk()
355 reg = readl(&mxc_ccm->cscdr1); in get_uart_clk()
369 u32 cscmr1 = readl(&mxc_ccm->cscmr1); in imx_get_cspiclk()
370 u32 cscdr2 = readl(&mxc_ccm->cscdr2); in imx_get_cspiclk()
386 u32 cscmr1 = readl(&mxc_ccm->cscmr1); in get_esdhc_clk()
387 u32 cscdr1 = readl(&mxc_ccm->cscdr1); in get_esdhc_clk()
420 u32 cbcdr = readl(&mxc_ccm->cbcdr); in get_axi_a_clk()
428 u32 cbcdr = readl(&mxc_ccm->cbcdr); in get_axi_b_clk()
436 u32 cbcdr = readl(&mxc_ccm->cbcdr); in get_emi_slow_clk()
449 u32 cbcmr = readl(&mxc_ccm->cbcmr); in get_ddr_clk()
452 u32 cbcdr = readl(&mxc_ccm->cbcdr); in get_ddr_clk()
518 return -EINVAL; in mxc_get_clock()
540 m -= n; in gcd()
564 "within [%d - %d]\n", in calc_pll_params()
567 return -EINVAL; in calc_pll_params()
578 return -EINVAL; in calc_pll_params()
586 return -EINVAL; in calc_pll_params()
594 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref; in calc_pll_params()
598 t1 -= n_ref * mfi; in calc_pll_params()
607 pll->pd = (u32)pd; in calc_pll_params()
608 pll->mfi = (u32)mfi; in calc_pll_params()
610 pll->mfn = (u32)mfn; in calc_pll_params()
612 pll->mfd = (u32)mfd; in calc_pll_params()
625 (v - 1); \
630 writel(0x1232, &pll->ctrl); \
631 writel(0x2, &pll->config); \
632 writel((((pd) - 1) << 0) | ((fi) << 4), \
633 &pll->op); \
634 writel(fn, &(pll->mfn)); \
635 writel((fd) - 1, &pll->mfd); \
636 writel((((pd) - 1) << 0) | ((fi) << 4), \
637 &pll->hfs_op); \
638 writel(fn, &pll->hfs_mfn); \
639 writel((fd) - 1, &pll->hfs_mfd); \
640 writel(0x1232, &pll->ctrl); \
641 while (!readl(&pll->ctrl) & 0x1) \
647 u32 ccsr = readl(&mxc_ccm->ccsr); in config_pll_clk()
654 &mxc_ccm->ccsr); in config_pll_clk()
655 CHANGE_PLL_SETTINGS(pll, pll_param->pd, in config_pll_clk()
656 pll_param->mfi, pll_param->mfn, in config_pll_clk()
657 pll_param->mfd); in config_pll_clk()
660 &mxc_ccm->ccsr); in config_pll_clk()
665 &mxc_ccm->ccsr); in config_pll_clk()
666 CHANGE_PLL_SETTINGS(pll, pll_param->pd, in config_pll_clk()
667 pll_param->mfi, pll_param->mfn, in config_pll_clk()
668 pll_param->mfd); in config_pll_clk()
671 &mxc_ccm->ccsr); in config_pll_clk()
676 &mxc_ccm->ccsr); in config_pll_clk()
677 CHANGE_PLL_SETTINGS(pll, pll_param->pd, in config_pll_clk()
678 pll_param->mfi, pll_param->mfn, in config_pll_clk()
679 pll_param->mfd); in config_pll_clk()
682 &mxc_ccm->ccsr); in config_pll_clk()
688 &mxc_ccm->ccsr); in config_pll_clk()
689 CHANGE_PLL_SETTINGS(pll, pll_param->pd, in config_pll_clk()
690 pll_param->mfi, pll_param->mfn, in config_pll_clk()
691 pll_param->mfd); in config_pll_clk()
694 &mxc_ccm->ccsr); in config_pll_clk()
698 return -EINVAL; in config_pll_clk()
712 /* The case that periph uses PLL1 is not considered here */ in config_core_clk()
728 return -EINVAL; in config_nfc_clk()
734 clrsetbits_le32(&mxc_ccm->cbcdr, in config_nfc_clk()
736 MXC_CCM_CBCDR_NFC_PODF(div - 1)); in config_nfc_clk()
737 while (readl(&mxc_ccm->cdhipr) != 0) in config_nfc_clk()
746 clrsetbits_le32(&mxc_ccm->CCGR5, in enable_nfc_clk()
755 setbits_le32(&mxc_ccm->cgpr, in enable_efuse_prog_supply()
758 clrbits_le32(&mxc_ccm->cgpr, in enable_efuse_prog_supply()
771 if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { in config_periph_clk()
779 readl(&mxc_ccm->cbcmr))) { in config_periph_clk()
787 return -EINVAL; in config_periph_clk()
798 u32 cbcmr = readl(&mxc_ccm->cbcmr); in config_ddr_clk()
823 return -EINVAL; in config_ddr_clk()
833 clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift); in config_ddr_clk()
834 while (readl(&mxc_ccm->cdhipr) != 0) in config_ddr_clk()
836 writel(0x0, &mxc_ccm->ccdr); in config_ddr_clk()
862 return -EINVAL; in config_ldb_clk()
876 * Note 1) There is no value checking for the passed-in divider values
893 return -EINVAL; in mxc_set_clock()
897 return -EINVAL; in mxc_set_clock()
901 return -EINVAL; in mxc_set_clock()
905 return -EINVAL; in mxc_set_clock()
909 return -EINVAL; in mxc_set_clock()
926 * '00' - 100MHz (External)
927 * '01' - 50MHz (External)
928 * '10' - 120MHz, internal (USB PHY)
929 * '11' - Reserved
951 printf("PLL1 %8d MHz\n", freq / 1000000); in do_mx5_showclocks()