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/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A Dapple,cluster-cpufreq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple SoC cluster cpufreq device
10 - Hector Martin <marcan@marcan.st>
13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
14 the cluster management register block. This binding uses the standard
15 operating-points-v2 table to define the CPU performance states, with the
16 opp-level property specifying the hardware p-state index for that level.
[all …]
/openbmc/linux/drivers/clk/mvebu/
H A Dap-cpu-clk.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell Armada AP CPU Clock Controller
11 #define pr_fmt(fmt) "ap-cpu-clk: " fmt
13 #include <linux/clk-provider.h>
33 * struct cpu_dfs_regs: CPU DFS register mapping
34 * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
53 /* AP806 CPU DFS register mapping*/
91 /* AP807 CPU DFS register mapping */
127 * struct ap806_clk: CPU cluster clock controller instance
128 * @cluster: Cluster clock controller index
[all …]
/openbmc/linux/arch/x86/kernel/apic/
H A Dx2apic_cluster.c1 // SPDX-License-Identifier: GPL-2.0
17 * Using per cpu variable would cost one cache line per cpu.
29 static void x2apic_send_IPI(int cpu, int vector) in x2apic_send_IPI() argument
31 u32 dest = x86_cpu_to_logical_apicid[cpu]; in x2apic_send_IPI()
41 unsigned int cpu, clustercpu; in __x2apic_send_IPI_mask() local
52 /* If IPI should not be sent to self, clear current CPU */ in __x2apic_send_IPI_mask()
56 /* Collapse cpus in a cluster so a single IPI per cluster is sent */ in __x2apic_send_IPI_mask()
57 for_each_cpu(cpu, tmpmsk) { in __x2apic_send_IPI_mask()
58 struct cpumask *cmsk = per_cpu(cluster_masks, cpu); in __x2apic_send_IPI_mask()
68 /* Remove cluster CPUs from tmpmask */ in __x2apic_send_IPI_mask()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-topology.txt2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
[all …]
/openbmc/linux/arch/arm/mach-versatile/
H A Dspc.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
14 #include <linux/cpu.h>
28 #define SPCLOG "vexpress-spc: "
39 /* SPC wake-up IRQs status and mask */
46 /* SPC per-CPU mailboxes */
50 /* SPC CPU/cluster reset statue */
52 #define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu)) argument
53 #define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu))) argument
68 /* wake-up interrupt masks */
[all …]
/openbmc/linux/drivers/perf/
H A Dqcom_l2_pmu.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2017 The Linux Foundation. All rights reserved.
26 #include <soc/qcom/kryo-l2-accessors.h>
121 * The cache is made up of one or more clusters, each cluster has its own PMU.
122 * Each cluster is associated with one or more CPUs.
125 * Events can be envisioned as a 2-dimensional array. Each column represents
143 /* The CPU that is used for collecting events on this cluster */
145 /* All the CPUs associated with this cluster */
164 struct l2cache_pmu *l2cache_pmu, int cpu) in get_cluster_pmu() argument
166 return *per_cpu_ptr(l2cache_pmu->pmu_cluster, cpu); in get_cluster_pmu()
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/openbmc/linux/arch/mips/kernel/
H A Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0-only
10 leaf->type = c_type; \
11 leaf->level = c_level; \
12 leaf->coherency_line_size = c->cache.linesz; \
13 leaf->number_of_sets = c->cache.sets; \
14 leaf->ways_of_associativity = c->cache.ways; \
15 leaf->size = c->cache.linesz * c->cache.sets * \
16 c->cache.ways; \
20 int init_cache_level(unsigned int cpu) in init_cache_level() argument
23 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); in init_cache_level()
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/openbmc/u-boot/arch/arm/cpu/armv8/
H A DKconfig15 bool "Enable multiple CPUs to enter into U-Boot"
18 bool "Enable data coherency with other cores in cluster"
21 CPUECTLR_EL1.SMPEN bit before U-Boot.
24 cluster, and for A57/A72, it enables receiving of instruction
33 or when CPU implementation doesn't include that register.
36 bool "Support spin-table enable method"
39 Say Y here to support "spin-table" enable method for booting Linux.
42 - Specify enable-method = "spin-table" in each CPU node in the
44 - Bring secondary CPUs into U-Boot proper in a board specific
47 master CPU protects the relocated spin code.
[all …]
/openbmc/linux/Documentation/admin-guide/pm/
H A Dintel_uncore_frequency_scaling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 :Copyright: |copy| 2022-2023 Intel Corporation
13 ------------
22 the scaling min/max frequencies via cpufreq sysfs to improve CPU performance.
30 ---------------
33 `/sys/devices/system/cpu/intel_uncore_frequency/`.
36 uncore scaling control is per die in multiple die/package SoCs or per
37 package for single die per package SoCs. The name represents the
45 This is a read-only attribute. If users adjust max_freq_khz,
50 This is a read-only attribute. If users adjust min_freq_khz,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dap80x-system-controller.txt6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
[all …]
/openbmc/linux/arch/arm/include/asm/
H A Dmcpm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright: (C) 2012-2013 Linaro Limited
13 * Maximum number of possible clusters / CPUs per cluster.
39 * This is used to indicate where the given CPU from given cluster should
40 * branch once it is ready to re-enter the kernel using ptr, or NULL if it
41 * should be gated. A gated CPU is held in a WFE loop until its vector
44 void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr);
48 * from very early assembly code before the CPU is ungated. The
51 void mcpm_set_early_poke(unsigned cpu, unsigned cluster,
55 * CPU/cluster power operations API for higher subsystems to use.
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/openbmc/linux/include/linux/
H A Dswap.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <linux/page-flags.h>
29 #define SWAP_FLAG_DISCARD_ONCE 0x20000 /* discard swap area at swapon-time */
30 #define SWAP_FLAG_DISCARD_PAGES 0x40000 /* discard page-clusters after use */
39 return current->flags & PF_KSWAPD; in current_is_kswapd()
47 * on 32-bit-pgoff_t architectures. And that assumes that the architecture packs
70 * device memory that is unaddressable (inaccessible) by CPU, so that we can
73 * When a page is migrated from CPU to device, we set the CPU page table entry
76 * When a page is mapped by the device for exclusive access we set the CPU page
118 ((1 << MAX_SWAPFILES_SHIFT) - SWP_DEVICE_NUM - \
[all …]
H A Dcpu_pm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * When a CPU goes to a low power state that turns off power to the CPU's
25 * The notifications are split into two classes: CPU notifications and CPU
26 * cluster notifications.
28 * CPU notifications apply to a single CPU and must be called on the affected
29 * CPU. They are used to save per-cpu context for affected blocks.
31 * CPU cluster notifications apply to all CPUs in a single power domain. They
41 /* A single cpu is entering a low power state */
44 /* A single cpu failed to enter a low power state */
47 /* A single cpu is exiting a low power state */
[all …]
/openbmc/linux/Documentation/ABI/stable/
H A Dsysfs-devices-system-cpu1 What: /sys/devices/system/cpu/dscr_default
2 Date: 13-May-2014
6 /sys/devices/system/cpu/cpuN/dscr on all CPUs.
9 all per-CPU defaults at the same time.
12 What: /sys/devices/system/cpu/cpu[0-9]+/dscr
13 Date: 13-May-2014
17 a CPU.
22 on any CPU where it executes (overriding the value described
27 What: /sys/devices/system/cpu/cpuX/topology/physical_package_id
33 What: /sys/devices/system/cpu/cpuX/topology/die_id
[all …]
/openbmc/linux/drivers/cpufreq/
H A Dtegra194-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020 - 2022, NVIDIA CORPORATION. All rights reserved
6 #include <linux/cpu.h>
9 #include <linux/dma-mapping.h>
20 #include <soc/tegra/bpmp-abi.h>
30 #define CORE_OFFSET(cpu) (cpu * 8) argument
32 #define SCRATCH_FREQ_CORE_REG(data, cpu) (data->regs + CMU_CLKS_BASE + CORE_OFFSET(cpu)) argument
36 (data->regs + (MMCRAB_CLUSTER_BASE(cl) + data->soc->actmon_cntr_base))
37 #define CORE_ACTMON_CNTR_REG(data, cl, cpu) (CLUSTER_ACTMON_BASE(data, cl) + CORE_OFFSET(cpu)) argument
43 u32 cpu; member
[all …]
H A Dvexpress-spc-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2019 ARM Ltd.
15 #include <linux/cpu.h>
45 #define ACTUAL_FREQ(cluster, freq) ((cluster == A7_CLUSTER) ? freq << 1 : freq) argument
46 #define VIRT_FREQ(cluster, freq) ((cluster == A7_CLUSTER) ? freq >> 1 : freq) argument
60 static inline int raw_cpu_to_cluster(int cpu) in raw_cpu_to_cluster() argument
62 return topology_physical_package_id(cpu); in raw_cpu_to_cluster()
65 static inline int cpu_to_cluster(int cpu) in cpu_to_cluster() argument
68 MAX_CLUSTERS : raw_cpu_to_cluster(cpu); in cpu_to_cluster()
71 static unsigned int find_cluster_maxfreq(int cluster) in find_cluster_maxfreq() argument
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dsec_boot.S1 /* SPDX-License-Identifier: GPL-2.0+ */
8 #include <asm/arch/cpu.h>
16 ldmia r0!, {r3-r6}
17 stmia r2!, {r3-r6}
30 * (Base Address - 0x02020000, Limit Address - 0x020740000).
32 * U-Boot and kernel are aware of this code and flags by the simple
35 * values in both kernel and U-Boot for our use.
40 * These addresses are being used as flags in u-boot and kernel.
43 * Resume address - 0x2073008
44 * Resume flag - 0x207300C
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A Dl1d_cache.json4 …ns that missed in the level 1 data cache. This event only counts one event per cache line. This ev…
8 …fied memory structures, for example refill buffers, write buffers, and write-back buffers, are als…
12 …-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache…
28 … read operation misses in the level 1 data cache. This event only counts one event per cache line."
32 …write operation misses in the level 1 data cache. This event only counts one event per cache line."
36 …cache refills where the cache line data came from caches inside the immediate cluster of the core."
40 …he refills for which the cache line data came from outside the immediate cluster of the core, like…
48 …cDescription": "Counts write-backs from the level 1 data cache that are a result of a coherency op…
52 …- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast cache coheren…
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dl1d_cache.json4 …ns that missed in the level 1 data cache. This event only counts one event per cache line. This ev…
8 …fied memory structures, for example refill buffers, write buffers, and write-back buffers, are als…
12 …-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache…
24 … read operation misses in the level 1 data cache. This event only counts one event per cache line."
28 …write operation misses in the level 1 data cache. This event only counts one event per cache line."
32 …cache refills where the cache line data came from caches inside the immediate cluster of the core."
36 …he refills for which the cache line data came from outside the immediate cluster of the core, like…
44 …cDescription": "Counts write-backs from the level 1 data cache that are a result of a coherency op…
48 …- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast cache coheren…
/openbmc/linux/Documentation/admin-guide/perf/
H A Dqcom_l2_pmu.rst2 Qualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU)
7 own PMU. Each cluster has one or more CPUs associated with it.
17 Events can be envisioned as a 2-dimensional array. Each column represents
23 the code (array row) and G specifies the group (column) 0-7.
29 consisting of one CPU per cluster which will be used to handle all the PMU
30 events on that cluster.
34 perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1
36 perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1
39 not work. Per-task perf sessions are not supported.
/openbmc/linux/arch/x86/kvm/svm/
H A Davic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
19 #include <linux/amd-iommu.h>
60 static_assert(__AVIC_GATAG(AVIC_VM_ID_MASK, AVIC_VCPU_ID_MASK) == -1u);
81 struct list_head node; /* Used by SVM for per-vcpu ir_list */
87 struct vmcb *vmcb = svm->vmcb01.ptr; in avic_activate_vmcb()
89 vmcb->control.int_ctl &= ~(AVIC_ENABLE_MASK | X2APIC_MODE_MASK); in avic_activate_vmcb()
90 vmcb->control.avic_physical_id &= ~AVIC_PHYSICAL_MAX_INDEX_MASK; in avic_activate_vmcb()
92 vmcb->control.int_ctl |= AVIC_ENABLE_MASK; in avic_activate_vmcb()
95 * Note: KVM supports hybrid-AVIC mode, where KVM emulates x2APIC MSR in avic_activate_vmcb()
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/pmc.h>
16 #include <asm/arch-tegra/ap.h>
17 #include "../cpu.h"
19 /* Tegra124-specific CPU init code */
27 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ in enable_cpu_power_rail()
34 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), in enable_cpu_power_rail()
35 * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h). in enable_cpu_power_rail()
37 writel(0x7C830, &pmc->pmc_cpupwrgood_timer); in enable_cpu_power_rail()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,cci-400.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
19 space and multiple sets of interface control registers, one per slave
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
[all …]
/openbmc/openbmc/meta-security/recipes-ids/suricata/files/
H A Dsuricata.yaml2 ---
10 # conservative 1024. A higher number will make sure CPU's/CPU cores will be
13 # If you are using the CUDA pattern matcher (mpm-algo: ac-cuda), different rules
16 #max-pending-packets: 1024
18 # Runmode the engine should use. Please check --list-runmodes to get the available
27 # round-robin - Flows assigned to threads in a round robin fashion.
28 # active-packets - Flows assigned to threads that have the lowest number of
30 # hash - Flow alloted usihng the address hash. More of a random
33 #autofp-scheduler: active-packets
36 # it is a pure sniffing setup, set it to 'sniffer-only'.
[all …]

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