1*59809fe8SMauro Carvalho Chehab===================================================================== 2*59809fe8SMauro Carvalho ChehabQualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU) 3*59809fe8SMauro Carvalho Chehab===================================================================== 4*59809fe8SMauro Carvalho Chehab 5*59809fe8SMauro Carvalho ChehabThis driver supports the L2 cache clusters found in Qualcomm Technologies 6*59809fe8SMauro Carvalho ChehabCentriq SoCs. There are multiple physical L2 cache clusters, each with their 7*59809fe8SMauro Carvalho Chehabown PMU. Each cluster has one or more CPUs associated with it. 8*59809fe8SMauro Carvalho Chehab 9*59809fe8SMauro Carvalho ChehabThere is one logical L2 PMU exposed, which aggregates the results from 10*59809fe8SMauro Carvalho Chehabthe physical PMUs. 11*59809fe8SMauro Carvalho Chehab 12*59809fe8SMauro Carvalho ChehabThe driver provides a description of its available events and configuration 13*59809fe8SMauro Carvalho Chehaboptions in sysfs, see /sys/devices/l2cache_0. 14*59809fe8SMauro Carvalho Chehab 15*59809fe8SMauro Carvalho ChehabThe "format" directory describes the format of the events. 16*59809fe8SMauro Carvalho Chehab 17*59809fe8SMauro Carvalho ChehabEvents can be envisioned as a 2-dimensional array. Each column represents 18*59809fe8SMauro Carvalho Chehaba group of events. There are 8 groups. Only one entry from each 19*59809fe8SMauro Carvalho Chehabgroup can be in use at a time. If multiple events from the same group 20*59809fe8SMauro Carvalho Chehabare specified, the conflicting events cannot be counted at the same time. 21*59809fe8SMauro Carvalho Chehab 22*59809fe8SMauro Carvalho ChehabEvents are specified as 0xCCG, where CC is 2 hex digits specifying 23*59809fe8SMauro Carvalho Chehabthe code (array row) and G specifies the group (column) 0-7. 24*59809fe8SMauro Carvalho Chehab 25*59809fe8SMauro Carvalho ChehabIn addition there is a cycle counter event specified by the value 0xFE 26*59809fe8SMauro Carvalho Chehabwhich is outside the above scheme. 27*59809fe8SMauro Carvalho Chehab 28*59809fe8SMauro Carvalho ChehabThe driver provides a "cpumask" sysfs attribute which contains a mask 29*59809fe8SMauro Carvalho Chehabconsisting of one CPU per cluster which will be used to handle all the PMU 30*59809fe8SMauro Carvalho Chehabevents on that cluster. 31*59809fe8SMauro Carvalho Chehab 32*59809fe8SMauro Carvalho ChehabExamples for use with perf:: 33*59809fe8SMauro Carvalho Chehab 34*59809fe8SMauro Carvalho Chehab perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1 35*59809fe8SMauro Carvalho Chehab 36*59809fe8SMauro Carvalho Chehab perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1 37*59809fe8SMauro Carvalho Chehab 38*59809fe8SMauro Carvalho ChehabThe driver does not support sampling, therefore "perf record" will 39*59809fe8SMauro Carvalho Chehabnot work. Per-task perf sessions are not supported. 40