| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-riscv-intc.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
29 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
36 * On RISC-V systems local interrupts are masked or unmasked by writing
38 * on the local hart, these functions can only be called on the hart that
44 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
49 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
55 * Andes specific S-mode local interrupt causes (hwirq) in andes_intc_irq_mask()
56 * are defined as (256 + n) and controlled by n-th bit in andes_intc_irq_mask()
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
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| /openbmc/linux/arch/riscv/kernel/ |
| H A D | kexec_relocate.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019 FORTH-ICS/CARV
19 * s3: (const) The hartid of the current hart
21 * s5: (const) Number of words per page
63 REG_L t0, 0(s0) /* t0 = *image->entry */
64 addi s0, s0, RISCV_SZPTR /* image->entry++ */
66 /* IND_DESTINATION entry ? -> save destination address */
73 /* IND_INDIRECTION entry ? -> update next entry ptr (PA) */
82 /* IND_DONE entry ? -> jump to done label */
89 * IND_SOURCE entry ? -> copy page word by word to the
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| H A D | cpufeature.c | 1 // SPDX-License-Identifier: GPL-2.0-only
27 #include "copy-unaligned.h"
29 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
33 #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
40 /* Per-cpu ISA extensions. */
47 * riscv_isa_extension_base() - Get base extension word
63 * __riscv_isa_extension_available() - Check whether given extension
88 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_isa_extension_check()
91 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_isa_extension_check()
97 pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n"); in riscv_isa_extension_check()
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| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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| /openbmc/qemu/docs/system/riscv/ |
| H A D | virt.rst | 8 real-world hardware.
11 -----------------
17 * Platform-Level Interrupt Controller (PLIC)
22 * 8 virtio-mmio transport devices
31 ----------------------------------
34 which it passes to the guest, if there is no ``-dtb`` option. This provides
39 If users want to provide their own DTB, they can use the ``-dtb`` option.
42 * The number of subnodes of the /cpus node should match QEMU's ``-smp`` option
43 * The /memory reg size should match QEMU’s selected ram_size via ``-m``
48 ------------
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| /openbmc/linux/Documentation/riscv/ |
| H A D | boot.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
32 The RISC-V kernel expects:
37 -------------------------------------
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| /openbmc/qemu/hw/riscv/ |
| H A D | virt-acpi-build.c | 4 * RISC-V virt ACPI generation
6 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
10 * Copyright (C) 2021-2023 Ventana Micro Systems Inc
27 #include "hw/acpi/acpi-defs.h"
29 #include "hw/acpi/aml-build.h"
34 #include "hw/pci-host/gpex.h"
37 #include "hw/virtio/virtio-acpi.h"
40 #include "qemu/error-report.h"
69 uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); in riscv_acpi_madt_add_rintc()
70 uint64_t hart_id = arch_ids->cpus[uid].arch_id; in riscv_acpi_madt_add_rintc()
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| H A D | virt.c | 2 * QEMU RISC-V VirtIO Board
6 * RISC-V machine with 16550a UART and VirtIO MMIO
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial-mm.h"
32 #include "hw/core/sysbus-fdt.h"
45 #include "hw/platform-bus.h"
54 #include "hw/pci-host/gpex.h"
56 #include "hw/acpi/aml-build.h"
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| H A D | opentitan.c | 2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
25 #include "qemu/error-report.h"
37 * MMIO mapping as per (specified commit):
85 if (machine->ram_size != mc->default_ram_size) { in opentitan_machine_init()
86 char *sz = size_to_str(mc->default_ram_size); in opentitan_machine_init()
93 object_initialize_child(OBJECT(machine), "soc", &s->soc, in opentitan_machine_init()
95 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); in opentitan_machine_init()
98 memmap[IBEX_DEV_RAM].base, machine->ram); in opentitan_machine_init()
100 if (machine->firmware) { in opentitan_machine_init()
102 riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL); in opentitan_machine_init()
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| H A D | boot.c | 2 * QEMU RISC-V Boot Helper
23 #include "qemu/error-report.h"
24 #include "exec/cpu-defs.h"
39 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]); in riscv_is_32bit()
40 return mcc->misa_mxl_max == MXL_RV32; in riscv_is_32bit()
44 * Return the per-socket PLIC hart topology configuration string
54 CPURISCVState *env = &RISCV_CPU(cs)->env; in riscv_plic_hart_config_string()
101 error_report("Unable to find the RISC-V BIOS \"%s\"", in riscv_find_bios()
117 * The user didn't specify -bios, or has specified "-bios default". in riscv_find_firmware()
137 firmware_filename = riscv_find_firmware(machine->firmware, in riscv_find_and_load_firmware()
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| /openbmc/linux/drivers/cpuidle/ |
| H A D | cpuidle-riscv-sbi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V SBI CPU idle driver.
9 #define pr_fmt(fmt) "cpuidle-riscv-sbi: " fmt
52 data->available = true; in sbi_set_domain_state()
53 data->state = state; in sbi_set_domain_state()
60 return data->state; in sbi_get_domain_state()
67 data->available = false; in sbi_clear_domain_state()
74 return data->available; in sbi_is_domain_state_available()
115 u32 *states = data->states; in __sbi_enter_domain_idle_state()
116 struct device *pd_dev = data->dev; in __sbi_enter_domain_idle_state()
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| /openbmc/linux/Documentation/timers/ |
| H A D | highres.rst | 8 https://www.kernel.org/doc/ols/2006/ols2006v1-pages-333-346.pdf
11 http://www.cs.columbia.edu/~nahum/w6998/papers/ols2006-hrtimers-slides.pdf
23 - hrtimer base infrastructure
24 - timeofday and clock source management
25 - clock event management
26 - high resolution timer functionality
27 - dynamic ticks
31 ---------------------------
40 - time ordered enqueueing into a rb-tree
41 - independent of ticks (the processing is based on nanoseconds)
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| /openbmc/linux/arch/riscv/kvm/ |
| H A D | aia.c | 1 // SPDX-License-Identifier: GPL-2.0
38 raw_spin_lock_irqsave(&hgctrl->lock, flags); in aia_find_hgei()
40 hgei = -1; in aia_find_hgei()
42 if (hgctrl->owners[i] == owner) { in aia_find_hgei()
48 raw_spin_unlock_irqrestore(&hgctrl->lock, flags); in aia_find_hgei()
71 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_flush_interrupts()
77 if (READ_ONCE(vcpu->arch.irqs_pending_mask[1])) { in kvm_riscv_vcpu_aia_flush_interrupts()
78 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask[1], 0); in kvm_riscv_vcpu_aia_flush_interrupts()
79 val = READ_ONCE(vcpu->arch.irqs_pending[1]) & mask; in kvm_riscv_vcpu_aia_flush_interrupts()
81 csr->hviph &= ~mask; in kvm_riscv_vcpu_aia_flush_interrupts()
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| /openbmc/linux/drivers/clocksource/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
180 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
203 32-bit free running decrementing counters.
238 bool "Integrator-AP timer driver" if COMPILE_TEST
241 Enables support for the Integrator-AP timer.
266 available on many OMAP-like platforms.
285 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
289 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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| /openbmc/qemu/target/riscv/ |
| H A D | pmu.c | 2 * RISC-V PMU file.
21 #include "qemu/error-report.h"
25 #include "sysemu/cpu-timers.h"
34 * to provide the correct value as well. Heterogeneous PMU per hart is not
78 qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", in riscv_pmu_generate_fdt_node()
85 !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) { in riscv_pmu_counter_valid()
94 CPURISCVState *env = &cpu->env; in riscv_pmu_counter_enabled()
97 !get_field(env->mcountinhibit, BIT(ctr_idx))) { in riscv_pmu_counter_enabled()
106 CPURISCVState *env = &cpu->env; in riscv_pmu_incr_ctr_rv32()
108 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; in riscv_pmu_incr_ctr_rv32()
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| H A D | cpu_helper.c | 2 * RISC-V CPU helpers for qemu.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
22 #include "qemu/main-loop.h"
26 #include "exec/exec-all.h"
27 #include "exec/page-protection.h"
29 #include "tcg/tcg-op.h"
31 #include "semihosting/common-semi.h"
32 #include "sysemu/cpu-timers.h"
35 #include "tcg/oversized-guest.h"
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| H A D | csr.c | 2 * RISC-V Control and Status Registers.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
24 #include "tcg/tcg-cpu.h"
27 #include "exec/exec-all.h"
28 #include "exec/tb-flush.h"
29 #include "sysemu/cpu-timers.h"
30 #include "qemu/guest-random.h"
36 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; in riscv_get_csr_ops()
41 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; in riscv_set_csr_ops()
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| /openbmc/linux/Documentation/RCU/ |
| H A D | RTFP.txt | 4 This document describes RCU-related publications, and is followed by
19 with short-lived threads, such as the K42 research operating system.
20 However, Linux has long-lived tasks, so more is needed.
23 serialization, which is an RCU-like mechanism that relies on the presence
27 that these overheads were not so expensive in the mid-80s. Nonetheless,
28 passive serialization appears to be the first deferred-destruction
30 has lapsed, so this approach may be used in non-GPL software, if desired.
34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].
36 this paper helped inspire the update-side batching used in the later
38 a description of Argus that noted that use of out-of-date values can
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| /openbmc/linux/include/acpi/ |
| H A D | actbl2.h | 1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
4 * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec)
6 * Copyright (C) 2000 - 2023, Intel Corp.
51 #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */
59 * All tables must be byte-packed to match the ACPI specification, since
69 * essentially useless for dealing with packed data in on-disk formats or
78 * AEST - Arm Error Source Table
89 /* Common Subtable header - one per Node Structure (Subtable) */
246 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface
266 * APMT - ARM Performance Monitoring Unit Table
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| /openbmc/linux/drivers/platform/x86/ |
| H A D | wmi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ACPI-WMI mapping driver
5 * Copyright (C) 2007-2008 Carlos Corbacho <carlos@strangeworlds.co.uk>
9 * Copyright (c) 2001-2007 Anton Altaparmakov
12 * WMI bus infrastructure by Andrew Lutomirski and Darren Hart:
39 MODULE_DESCRIPTION("ACPI-WMI Mapping Driver");
107 "05901221-D566-11D1-B2F0-00A0C9062910", /* wmi-bmof */
108 "8A42EA14-4F2A-FD45-6422-0087F7A7E608", /* dell-wmi-ddv */
128 if (guid_equal(&wblock->gblock.guid, &guid_input)) { in find_guid()
154 id = wdriver->id_table; in find_guid_context()
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| /openbmc/linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
38 One pattern per line. Multiple F: lines acceptable.
46 N: [^a-z]tegra all files whose path contains tegra
48 One pattern per line. Multiple N: lines acceptable.
61 One regex pattern per line. Multiple K: lines acceptable.
64 ----------------
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