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/openbmc/u-boot/drivers/pci/
H A Dpcie_layerscape.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * Layerscape PCIe driver
25 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) in dbi_readl() argument
27 return in_le32(pcie->dbi + offset); in dbi_readl()
30 static void dbi_writel(struct ls_pcie *pcie, unsigned int value, in dbi_writel() argument
33 out_le32(pcie->dbi + offset, value); in dbi_writel()
36 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset) in ctrl_readl() argument
38 if (pcie->big_endian) in ctrl_readl()
39 return in_be32(pcie->ctrl + offset); in ctrl_readl()
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H A Dpci_tegra.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on NVIDIA PCIe driver
7 * Copyright (c) 2008-2009, NVIDIA Corporation.
9 * Copyright (c) 2013-2014, NVIDIA Corporation.
12 #define pr_fmt(fmt) "tegra-pcie: " fmt
21 #include <power-domain.h>
33 #include <asm/arch-tegra/xusb-padctl.h>
34 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
41 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
77 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
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H A Dpci_mvebu.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Marvell MVEBU SoCs
5 * Based on Barebox drivers/pci/pci-mvebu.c
7 * Ported to U-Boot by:
14 #include <dm/device-internal.h>
27 /* PCIe unit register offsets */
28 #define SELECT(x, n) ((x >> n) & 1UL)
38 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
84 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
91 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) in mvebu_pcie_link_up() argument
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H A Dpcie_dw_mvebu.c1 // SPDX-License-Identifier: GPL-2.0+
8 * - drivers/pci/pcie_imx.c
9 * - drivers/pci/pci_mvebu.c
10 * - drivers/pci/pcie_xilinx.c
17 #include <asm-generic/gpio.h>
65 #define GEN3_EQU_DISABLE (1 << 16)
66 #define GEN3_ZRXDC_NON_COMP (1 << 0)
69 #define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5)
76 #define PCIE_APP_LTSSM_EN (1 << 2)
84 #define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1)
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H A Dpci-aardvark.c20 * Ported from Linux driver - driver/pci/host/pci-aardvark.c
31 #include <asm-generic/gpio.h>
34 /* PCIe core registers */
37 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
59 #define PIO_COMPLETION_STATUS_UR 1
78 #define SPEED_GEN_2 1
80 #define IS_RC_MSK 1
85 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
102 /* PCIe core controller registers */
126 /* PCIe Retries & Timeout definitions */
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H A Dpcie_intel_fpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel FPGA PCIe host controller driver
5 * Copyright (C) 2013-2018 Intel Corporation. All rights reserved
17 #define RP_TX_EOP BIT(1)
20 #define RP_RXCPL_EOP BIT(1)
27 /* TLP configuration type 0 and 1 */
30 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
31 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
37 #define RP_CFG_ADDR(pcie, reg) \ argument
38 ((pcie->hip_base) + (reg) + (1 << 20))
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/openbmc/linux/drivers/pci/controller/
H A Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
86 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
87 #define AFI_CONFIGURATION_CLKEN_OVERRIDE (1 << 31)
92 #define AFI_INTR_MASK_INT_MASK (1 << 0)
93 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
97 #define AFI_INTR_INI_SLAVE_ERROR 1
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H A Dpcie-altera.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6 * Description: Altera PCIe host controller driver
44 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
45 (((pcie)->hip_base) + (reg) + (1 << 20))
46 #define S10_RP_SECONDARY(pcie) \ argument
47 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
49 /* TLP configuration type 0 and 1 */
52 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
53 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
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H A Dpcie-rcar-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe endpoint driver for Renesas R-Car SoCs
6 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 #include <linux/pci-epc.h>
17 #include "pcie-rcar.h"
19 #define RCAR_EPC_MAX_FUNCTIONS 1
21 /* Structure representing the PCIe interface */
23 struct rcar_pcie pcie; member
33 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument
37 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init()
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H A Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
40 /* Broadcom STB PCIe Register Offsets */
147 /* PCIe parameters */
152 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
154 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
169 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
170 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
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H A Dpci-aardvark.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
20 #include <linux/pci-ecam.h>
30 #include "../pci-bridge-emul.h"
32 /* PCIe core registers */
53 #define PIO_COMPLETION_STATUS_UR 1
73 #define SPEED_GEN_2 1
75 #define IS_RC_MSK 1
80 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
97 #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1)
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H A Dpcie-rcar-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
16 #include <linux/clk-provider.h>
33 #include "pcie-rcar.h"
44 /* Structure representing the PCIe interface */
46 struct rcar_pcie pcie; member
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H A Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
28 #define EP_MODE_SURVIVE_PERST_SHIFT 1
43 #define CFG_ADDR_CFG_TYPE_1 1
56 #define CFG_RD_UR 1
73 #define OARR_SIZE_CFG_SHIFT 1
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
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H A Dpcie-mediatek-gen3.c1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
43 #define PCIE_PHY_RSTB BIT(1)
61 #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
65 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
69 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
83 #define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1)
95 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
98 #define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1)
104 * struct mtk_msi_set - MSI information for each set
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
20 - enum:
21 - qcom,pcie-apq8064
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H A Dfsl,imx6q-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe RC/EP controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 Generic Freescale i.MX PCIe Root Port and Endpoint controller
22 clock-names:
26 num-lanes:
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H A Dmvebu-pci.txt1 * Marvell EBU PCIe interfaces
5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
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/openbmc/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Mobiveil PCIe Host controller
6 * Copyright 2019-2020 NXP
25 #include "pcie-mobiveil.h"
37 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
44 * mobiveil_pcie_map_bus - routine to get the configuration base of either
50 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
51 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
59 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
67 value = bus->number << PAB_BUS_SHIFT | in mobiveil_pcie_map_bus()
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H A Dpcie-mobiveil.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
21 * mobiveil_pcie_sel_page - routine to access paged register
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
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/openbmc/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe endpoint controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include <linux/pci-epc.h>
13 #include "pcie-cadence.h"
19 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument
27 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, f in cdns_pcie_get_fn_from_vfn()
39 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_write_header() local
81 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_set_bar() local
155 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_clear_bar() local
187 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_map_addr() local
209 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_unmap_addr() local
228 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_set_msi() local
250 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_get_msi() local
273 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_get_msix() local
294 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_set_msix() local
322 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_assert_intx() local
382 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_send_msi_irq() local
436 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_map_msi_irq() local
487 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_send_msix_irq() local
537 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_raise_irq() local
564 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_start() local
644 struct cdns_pcie *pcie = &ep->pcie; cdns_pcie_ep_setup() local
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H A Dpci-j721e.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
10 #include <linux/clk-provider.h>
25 #include "pcie-cadence.h"
27 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
32 #define LINK_DOWN BIT(1)
39 #define LINK_STATUS GENMASK(1, 0)
51 #define GENERATION_SEL_MASK GENMASK(1, 0)
72 unsigned int quirk_retrain_flag:1;
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/openbmc/linux/drivers/pci/controller/dwc/
H A Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for the following SoCs
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
35 #include "pcie-designware.h"
37 #include <soc/tegra/bpmp-abi.h>
54 #define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0)
76 #define APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN BIT(1)
81 #define APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED BIT(1)
90 #define APPL_INTR_STATUS_L1_15_CFG_BME_CHGED BIT(1)
113 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR BIT(1)
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H A Dpcie-intel-gw.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Intel Gateway SoCs
20 #include "pcie-designware.h"
22 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
26 /* PCIe Application logic Registers */
84 static inline void pcie_app_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_app_wr() argument
86 writel(val, pcie->app_base + ofs); in pcie_app_wr()
89 static void pcie_app_wr_mask(struct intel_pcie *pcie, u32 ofs, in pcie_app_wr_mask() argument
92 pcie_update_bits(pcie->app_base, ofs, mask, val); in pcie_app_wr_mask()
95 static inline u32 pcie_rc_cfg_rd(struct intel_pcie *pcie, u32 ofs) in pcie_rc_cfg_rd() argument
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H A Dpcie-qcom.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
27 #include <linux/phy/pcie.h>
35 #include "pcie-designware.h"
81 #define L1_CLK_RMV_DIS BIT(1)
112 #define MSTR_AXI_CLK_EN BIT(1)
139 #define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1)
152 #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
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