| /openbmc/linux/Documentation/devicetree/bindings/thermal/ |
| H A D | nvidia,tegra124-soctherm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 polled or interrupt-based thermal monitoring, CPU and GPU throttling based
21 - nvidia,tegra124-soctherm
22 - nvidia,tegra132-soctherm
23 - nvidia,tegra210-soctherm
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| /openbmc/linux/Documentation/devicetree/bindings/regulator/ |
| H A D | richtek,rt6245-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rt6245-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
13 The RT6245 is a high-performance, synchronous step-down converter
18 - $ref: regulator.yaml#
23 - richtek,rt6245
28 enable-gpios:
31 it will be treat as a default-on power.
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| /openbmc/linux/mm/ |
| H A D | oom_kill.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 * Since we won't call these routines often (on a well-configured
73 static inline bool is_memcg_oom(struct oom_control *oc) in is_memcg_oom() argument
75 return oc->memcg != NULL; in is_memcg_oom()
80 * oom_cpuset_eligible() - check task eligibility for kill
82 * @oc: pointer to struct oom_control
88 * This function is assuming oom-killer context and 'current' has triggered
89 * the oom-killer.
92 struct oom_control *oc) in oom_cpuset_eligible() argument
96 const nodemask_t *mask = oc->nodemask; in oom_cpuset_eligible()
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| /openbmc/qemu/hw/char/ |
| H A D | stm32l4x5_usart.c | 4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
22 #include "chardev/char-fe.h"
23 #include "chardev/char-serial.h"
28 #include "hw/qdev-clock.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
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| /openbmc/qemu/util/ |
| H A D | thread-context.c | 10 * See the COPYING file in the top-level directory.
14 #include "qemu/thread-context.h"
16 #include "qapi/qapi-builtin-visit.h"
18 #include "qemu/config-file.h"
19 #include "qapi/qapi-builtin-visit.h"
46 tc->thread_id = qemu_get_thread_id(); in thread_context_run()
47 qemu_sem_post(&tc->sem); in thread_context_run()
52 * reason, we create new (especially short-lived) threads from our in thread_context_run()
60 switch (tc->thread_cmd) { in thread_context_run()
64 tc->thread_cmd = TC_CMD_NONE; in thread_context_run()
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| /openbmc/linux/drivers/regulator/ |
| H A D | rt6245-regulator.c | 1 // SPDX-License-Identifier: GPL-2.0+
31 #define RT6245_NUM_VOUT ((RT6245_VOUT_MAXUV - RT6245_VOUT_MINUV) / RT6245_VOUT_STEPUV + 1)
44 if (!priv->enable_gpio) in rt6245_enable()
47 gpiod_direction_output(priv->enable_gpio, 1); in rt6245_enable()
55 priv->enable_state = true; in rt6245_enable()
64 if (!priv->enable_gpio) in rt6245_disable()
65 return -EINVAL; in rt6245_disable()
70 gpiod_direction_output(priv->enable_gpio, 0); in rt6245_disable()
72 priv->enable_state = false; in rt6245_disable()
80 return priv->enable_state ? 1 : 0; in rt6245_is_enabled()
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| H A D | da9121-regulator.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 // DA9121 Single-channel dual-phase 10A buck converter
7 // DA9130 Single-channel dual-phase 10A buck converter (Automotive)
8 // DA9217 Single-channel dual-phase 6A buck converter
9 // DA9122 Dual-channel single-phase 5A buck converter
10 // DA9131 Dual-channel single-phase 5A buck converter (Automotive)
11 // DA9220 Dual-channel single-phase 3A buck converter
12 // DA9132 Dual-channel single-phase 3A buck converter (Automotive)
30 #include "da9121-regulator.h"
136 int buck_id; /* 0=core, 1/2-buck */
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| /openbmc/qemu/hw/misc/ |
| H A D | mac_via.c | 4 * Copyright (c) 2011-2018 Laurent Vivier
5 * Copyright (c) 2018 Mark Cave-Ayland
9 * Copyright (c) 2004-2007 Fabrice Bellard
12 * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h
15 * See the COPYING file in the top-level directory.
19 #include "exec/address-spaces.h"
30 #include "hw/qdev-properties.h"
31 #include "hw/qdev-properties-system.h"
32 #include "sysemu/block-backend.h"
74 * Head select for IWM.
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| /openbmc/qemu/hw/arm/ |
| H A D | stellaris.c | 12 #include "hw/core/split-irq.h"
22 #include "exec/address-spaces.h"
28 #include "hw/watchdog/cmsdk-apb-watchdog.h"
31 #include "hw/timer/stellaris-gptm.h"
32 #include "hw/qdev-clock.h"
66 #define TYPE_STELLARIS_SYS "stellaris-sys"
87 /* Properties (all read-only registers) */
101 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
152 uint32_t did0 = s->did0; in ssys_board_class()
178 return s->did0; in ssys_read()
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| H A D | mps2-tz.c | 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524
20 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547
24 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
37 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
40 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines
43 * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM:
52 #include "qemu/error-report.h"
55 #include "hw/or-irq.h"
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| /openbmc/linux/drivers/thermal/tegra/ |
| H A D | soctherm.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
197 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
200 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
203 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
206 * level vector
212 #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1) argument
229 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
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| /openbmc/ipmitool/doc/ |
| H A D | ipmitool.1 | 3 ipmitool \- utility for controlling IPMI\-enabled devices
6 ipmitool [ <options> ] <command> [ <sub-commands and sub-options> ]
8 <options> := [ <general-options> | <conditional-opts> ]
13 <general-options> := [ -h | -V | -v | -I <interface> | -H <address> |
14 -d <N> | -p <port> | -c | -U <username> |
15 -L <privlvl> | -l <lun> | -m <local_address> |
16 -N <sec> | -R <count> | <password-option> |
17 <oem-option> | <bridge-options> ]
19 <conditional-opts> := [ <lan-options> | <lanplus-options> |
20 <command-options> ]
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| /openbmc/qemu/hw/block/ |
| H A D | swim.c | 4 * Copyright (c) 2014-2018 Laurent Vivier <laurent@vivier.eu>
7 * the COPYING file in the top-level directory.
14 #include "qemu/main-loop.h"
16 #include "sysemu/block-backend.h"
21 #include "hw/qdev-properties.h"
87 /* Select values for swim_select and swim_readbit */
155 blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort); in swim_change_cb()
157 if (!blkconf_apply_backend_options(drive->conf, in swim_change_cb()
158 !blk_supports_write_perm(drive->blk), in swim_change_cb()
170 DEFINE_PROP_INT32("unit", SWIMDrive, unit, -1),
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| /openbmc/qemu/hw/sh4/ |
| H A D | sh7750_regs.h | 2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
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| /openbmc/qemu/hw/riscv/ |
| H A D | sifive_u.c | 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
11 * 1) CLINT (Core Level Interruptor)
12 * 2) PLIC (Platform Level Interrupt Controller)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
39 #include "qemu/error-report.h"
99 uint64_t mem_size = ms->ram_size; in create_fdt()
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()
122 "sifive,hifive-unleashed-a00"); in create_fdt()
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| H A D | microchip_pfsoc.c | 2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
11 * 0) CLINT (Core Level Interruptor)
12 * 1) PLIC (Platform Level Interrupt Controller)
13 * 2) eNVM (Embedded Non-Volatile Memory)
14 * 3) MMUARTs (Multi-Mode UART)
38 #include "qemu/error-report.h"
59 * See https://github.com/polarfire-soc/hart-software-services
76 * https://www.microsemi.com/document-portal/doc_download/
77 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
81 * https://www.microsemi.com/document-portal/doc_download/
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| /openbmc/linux/sound/soc/codecs/ |
| H A D | ak4613.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // ak4613.c -- Asahi Kasei ALSA Soc Audio driver
14 * +-------+
16 * SDTO1 <-| |
18 * SDTI1 ->| |
19 * SDTI2 ->| |
20 * SDTI3 ->| |
21 * +-------+
23 * +---+
68 * +-----+ +-----------+
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| /openbmc/qemu/target/i386/kvm/ |
| H A D | kvm.c | 4 * Copyright (C) 2006-2008 Qumranet Technologies
11 * See the COPYING file in the top-level directory.
16 #include "qapi/qapi-events-run-state.h"
28 #include "standard-headers/asm-x86/kvm_para.h"
29 #include "hw/xen/interface/arch-x86/cpuid.h"
32 #include "host-cpu.h"
39 #include "../confidential-guest.h"
41 #include "xen-emu.h"
43 #include "hyperv-proto.h"
46 #include "qemu/host-utils.h"
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| /openbmc/linux/drivers/net/ethernet/marvell/ |
| H A D | skge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
268 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
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| /openbmc/openbmc/meta-arm/meta-arm-bsp/documentation/corstone1000/ |
| H A D | user-guide.rst | 2 # Copyright (c) 2022-2024, Arm Limited.
4 # SPDX-License-Identifier: MIT
11 ------
12 The Corstone-1000 software stack uses the `Yocto Project <https://www.yoctoproject.org/>`__ to build
13 a tiny Linux distribution suitable for the Corstone-1000 platform (kernel and initramfs filesystem …
14 The Yocto Project relies on the `BitBake <https://docs.yoctoproject.org/bitbake.html#bitbake-docume…
19 -------------
26 - Git 1.8.3.1 or greater.
27 - Python 3.8.0 or greater.
28 - GNU Tar 1.28 or greater.
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| /openbmc/qemu/target/arm/ |
| H A D | cpu.h | 23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-defs.h"
29 #include "exec/page-protection.h"
30 #include "qapi/qapi-types-common.h"
79 /* ARM-specific interrupt pending bits. */
102 /* ARM-specific extra insn start words:
113 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
148 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
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| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | drxk_hard.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drxk_hard: DRX-K DVB-C/T demodulator driver
5 * Copyright (C) 2010-2011 Digital Devices GmbH
45 return state->m_operation_mode == OM_DVBT; in is_dvbt()
50 return state->m_operation_mode == OM_QAM_ITU_A || in is_qam()
51 state->m_operation_mode == OM_QAM_ITU_B || in is_qam()
52 state->m_operation_mode == OM_QAM_ITU_C; in is_qam()
153 #define dprintk(level, fmt, arg...) do { \ argument
154 if (debug >= level) \
164 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ in Frac28a()
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| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_rps.c | 1 // SPDX-License-Identifier: MIT
43 return rps_to_gt(rps)->i915; in rps_to_i915()
48 return rps_to_gt(rps)->uncore; in rps_to_uncore()
55 return >->uc.guc.slpc; in rps_to_slpc()
62 return intel_uc_uses_guc_slpc(>->uc); in rps_uses_slpc()
67 return mask & ~rps->pm_intrmsk_mbz; in rps_pm_sanitize_mask()
90 last = engine->stats.rps; in rps_timer()
91 engine->stats.rps = dt; in rps_timer()
99 last = rps->pm_timestamp; in rps_timer()
100 rps->pm_timestamp = timestamp; in rps_timer()
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| /openbmc/linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
37 F: */net/* all files in "any top level directory"/net
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
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| H A D | opengrok1.0.log | 1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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