Revision tags: v9.2.0, v9.1.2, v9.1.1 |
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#
28ae3179 |
| 13-Sep-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-target-arm-20240913' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * s390: convert s390 virtio-ccw and CPU to three-phase reset * reset: remove
Merge tag 'pull-target-arm-20240913' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * s390: convert s390 virtio-ccw and CPU to three-phase reset * reset: remove now-unused device_class_set_parent_reset() * reset: introduce device_class_set_legacy_reset() * reset: remove unneeded transitional machinery * kvm: Use 'unsigned long' for request argument in functions wrapping ioctl() * hvf: arm: Implement and use hvf_get_physical_address_range so VMs can have larger-than-36-bit IPA spaces when the host supports this * target/arm/tcg: refine cache descriptions with a wrapper * hw/net/can/xlnx-versal-canfd: fix various bugs * MAINTAINERS: update versal, CAN maintainer entries * hw/intc/arm_gic: fix spurious level triggered interrupts
# -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmbkVokZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pR5D/0ZJzJi7C0HIa4KYuBkcpZQ # M3iUa1uiZoCniXlWuKFt2rUBrmhbW30YHw5gQjnxoUO4VVqREkFi3e5nzUKRQmvP # FRm8dnuC36qwQJFhm+rQqUb8/AyqrVFnIaHhn7dBKLwRFm9+kbZ0v9x1Eq1DZk3S # mijBQRiOjrj+FRkmyNJLhylGpm+p9VRdnBjmUtN2Yw+2fPkHmUURRSUvhwCK4BB5 # AvKgMC0EIIsLJKLfrWzk/EsYC8ogrGitISzFt8iWLAqxuxtuhv1StstleD4mZMK8 # gH+ZH5tsls2IiTIKkHfcbUcA55efDrQHGDat7n1Q0EWqOjET0soES+GpS0Jj6IXK # uOnsDZ7MLFU/SbpckicLQ/JwNi3HiIfQgBVB2aJZ+cg8CGqaQCI5ZvWs7XFpUgkb # naA4IR5mdNgXJm7ttBKbWarPNcmdODqa/5YDjXdyHmMx3JD994k1y5LIi3o69TgI # rgHzU8ChZqaBDEvNa5KGtadQPnaSBP15Yqbp5rn2knVRKjDdyCdB94aWO5tZkmaO # ARFmNk6h5bhwXdXl2Hu67RS2Kd0/fHMFWsxyHAX4NYT+Vq+ZTjLdaPzwFdfA0yAz # wXWn0EAeYQ5M2xOPfDM/JYSc1THSzhpwy/CBrRjrCRZMDE+bx9BRC7pUXwquE8xF # CW1NUxkvZikQeiMzgEBbTA== # =u6u8 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 13 Sep 2024 16:13:13 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20240913' of https://git.linaro.org/people/pmaydell/qemu-arm: (27 commits) hw/intc/arm_gic: fix spurious level triggered interrupts MAINTAINERS: Add my-self as CAN maintainer MAINTAINERS: Update Xilinx Versal OSPI maintainer's email address MAINTAINERS: Remove Vikram Garhwal as maintainer hw/net/can/xlnx-versal-canfd: Fix FIFO issues hw/net/can/xlnx-versal-canfd: Simplify DLC conversions hw/net/can/xlnx-versal-canfd: Fix byte ordering hw/net/can/xlnx-versal-canfd: Handle flags correctly hw/net/can/xlnx-versal-canfd: Translate CAN ID registers hw/net/can/xlnx-versal-canfd: Fix CAN FD flag check hw/net/can/xlnx-versal-canfd: Fix interrupt level target/arm/tcg: refine cache descriptions with a wrapper hvf: arm: Implement and use hvf_get_physical_address_range hvf: Split up hv_vm_create logic per arch hw/boards: Add hvf_get_physical_address_range to MachineClass kvm: Use 'unsigned long' for request argument in functions wrapping ioctl() hw/core/resettable: Remove transitional_function machinery hw/core/qdev: Simplify legacy_reset handling hw: Remove device_phases_reset() hw: Rename DeviceClass::reset field to legacy_reset ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
e3d08143 |
| 13-Sep-2024 |
Peter Maydell <peter.maydell@linaro.org> |
hw: Use device_class_set_legacy_reset() instead of opencoding
Use device_class_set_legacy_reset() instead of opencoding an assignment to DeviceClass::reset. This change was produced with: spatch --
hw: Use device_class_set_legacy_reset() instead of opencoding
Use device_class_set_legacy_reset() instead of opencoding an assignment to DeviceClass::reset. This change was produced with: spatch --macro-file scripts/cocci-macro-file.h \ --sp-file scripts/coccinelle/device-reset.cocci \ --keep-comments --smpl-spacing --in-place --dir hw
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240830145812.1967042-8-peter.maydell@linaro.org
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Revision tags: v9.1.0 |
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d328fef9 |
| 04-Jan-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-20231230' of https://gitlab.com/rth7680/qemu into staging
Mark VMStateField and VMStateDescription arrays const.
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXA
Merge tag 'pull-20231230' of https://gitlab.com/rth7680/qemu into staging
Mark VMStateField and VMStateDescription arrays const.
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmWPOFsdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8cCQgAnQjy3Ic1i225AElh # 0Ph3Aiw6WT9pECLoKmyroxHbTGuaEJoIXeaOhMAnowCTBLoKRR3/Ooq0DGOW+l/Z # f5PwWSkjkb+OcS+dj/kgQBu58/Gk5G8ogksqKQvci8k2okhjHmITSQDu0dtwzDZr # jVGh3gmGoat73jQyD/nAwgWFawlLkklOMR/yvnFX7EJIBepRVbkMPayoKlB+6W07 # 1kqhSwoI0vQCjhJ3Q7Q0GC4rrHK3KUq7o/25yvICf4EgPKfsaym1wAjDhdKToixl # 9T+ALZG8SiZZkBlb6l3QZ7pqtqavxYtPdZ2Gx/nMu0RRu4G33d5AVGHRrXj9qttW # 5mL7ZQ== # =uQ4C # -----END PGP SIGNATURE----- # gpg: Signature made Fri 29 Dec 2023 21:21:31 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-20231230' of https://gitlab.com/rth7680/qemu: (71 commits) docs: Constify VMstate in examples tests/unit/test-vmstate: Constify VMState util/fifo8: Constify VMState replay: Constify VMState system: Constify VMState migration: Constify VMState cpu-target: Constify VMState backends: Constify VMState audio: Constify VMState hw/misc/macio: Constify VMState hw/watchdog: Constify VMState hw/virtio: Constify VMState hw/vfio: Constify VMState hw/usb: Constify VMState hw/tpm: Constify VMState hw/timer: Constify VMState hw/ssi: Constify VMState hw/sparc: Constify VMState hw/sensor: Constify VMState hw/sd: Constify VMState ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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7d5dc0a3 |
| 20-Dec-2023 |
Richard Henderson <richard.henderson@linaro.org> |
hw/block: Constify VMState
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-25-richard.henderson@linaro.org>
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f7294103 |
| 09-Oct-2023 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'q800-for-8.2-pull-request' of https://github.com/vivier/qemu-m68k into staging
Pull request q800 20231008
add support for booting: - MacOS 7.1 - 8.1, with or without virtual memory ena
Merge tag 'q800-for-8.2-pull-request' of https://github.com/vivier/qemu-m68k into staging
Pull request q800 20231008
add support for booting: - MacOS 7.1 - 8.1, with or without virtual memory enabled - A/UX 3.0.1 - NetBSD 9.3 - Linux (via EMILE)
# -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmUiSrISHGxhdXJlbnRA # dml2aWVyLmV1AAoJEPMMOL0/L748oSUQAKAm3TPYQUDDVFTi2uhzv6IgNSgOVUhK # 3I3xoNb0UR9AT3Wfg1fah5La3p0kL9Y25gvhCl6veUg39WVicv3fbqUevbJ1Nwgl # ovwS3MRRcvYhU+omcXImFfoIPyOxfSf3vZ6SedIkB24hQyXN9eFBZMfgCODU6lfo # rAd/Hm50N2jRI8aKjvN+uHFRz75wqq6rNk/4QLWihRqhtWrjUDPHOTMI9sQxWy9z # LcXxVKbWCY8/WOAandsGL94l2jfu94HM6CfwHaumdxvPBZT6WUyCv3T1rJsVJU29 # b8oTLcwKAmZ7lGLbjl6GdB8q5KAJFCAGLWuEbNIMj0orB37OpUd0Wx2SD9+aA53H # yoKGbk6N1UappTtcnZCfwzWRzNaXrRno+w+/xYjlKsXBdHV9ZXHMGD5ERxoC6MY7 # ISsCa4bafeUDes6SCetgq87ho69E8l+gAlNYPgidHaTP226BjrYWQRJIa0leczfO # aE6dAG7MQFOnOjeOHEJMDB2XpKHiVe1lyVGQH485cLW1J6LHJFWUfUUH2Zjs1v1z # eXZHBTclPO2wbuQzXG6pAz2jdF/9w4ft/aA0PQhQcFxa9RB6AoNFG/juHJN5eUiw # NXJetR2g1juNPqmMFWDNMJ7Zzce5Chjoj69XJBFYSXhgbOtwpUpoEPZUeIMcW1eJ # Va2HvyDQPp1B # =RUHg # -----END PGP SIGNATURE----- # gpg: Signature made Sun 08 Oct 2023 02:22:42 EDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* tag 'q800-for-8.2-pull-request' of https://github.com/vivier/qemu-m68k: mac_via: extend timer calibration hack to work with A/UX q800: add alias for MacOS toolbox ROM at 0x40000000 q800: add ESCC alias at 0xc000 mac_via: always clear ADB interrupt when switching to A/UX mode mac_via: implement ADB_STATE_IDLE state if shift register in input mode mac_via: workaround NetBSD ADB bus enumeration issue mac_via: work around underflow in TimeDBRA timing loop in SETUPTIMEK swim: update IWM/ISM register block decoding swim: split into separate IWM and ISM register blocks swim: add trace events for IWM and ISM registers q800: add easc bool machine class property to switch between ASC and EASC q800: add Apple Sound Chip (ASC) audio to machine asc: generate silence if FIFO empty but engine still running audio: add Apple Sound Chip (ASC) emulation q800: allow accesses to RAM area even if less memory is available q800: add IOSB subsystem q800: implement additional machine id bits on VIA1 port A q800: add machine id register q800: add djMEMC memory controller q800-glue.c: convert to Resettable interface
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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994af0b2 |
| 04-Oct-2023 |
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> |
swim: update IWM/ISM register block decoding
Update the IWM/ISM register block decoding to match the description given in the "SWIM Chip Users Reference". This allows us to validate the device respo
swim: update IWM/ISM register block decoding
Update the IWM/ISM register block decoding to match the description given in the "SWIM Chip Users Reference". This allows us to validate the device response to the guest OS which currently only does just enough to indicate that the floppy drive is unavailable.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20231004083806.757242-14-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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57004204 |
| 04-Oct-2023 |
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> |
swim: split into separate IWM and ISM register blocks
The swim chip provides an implementation of both Apple's IWM and ISM floppy disk controllers. Split the existing implementation into separate re
swim: split into separate IWM and ISM register blocks
The swim chip provides an implementation of both Apple's IWM and ISM floppy disk controllers. Split the existing implementation into separate register banks for each controller, whilst also switching the IWM registers from 16-bit to 8-bit as implemented in real hardware.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20231004083806.757242-13-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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d05cad2b |
| 04-Oct-2023 |
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> |
swim: add trace events for IWM and ISM registers
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20231004083806.757242-12
swim: add trace events for IWM and ISM registers
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20231004083806.757242-12-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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Revision tags: v8.0.0, v7.2.0, v7.0.0, v6.2.0 |
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bb4aa8f5 |
| 30-Sep-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210930' into staging
target-arm queue: * allwinner-h3: Switch to SMC as PSCI conduit * arm: tcg: Adhere to SMCCC 1.3 section 5
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210930' into staging
target-arm queue: * allwinner-h3: Switch to SMC as PSCI conduit * arm: tcg: Adhere to SMCCC 1.3 section 5.2 * xlnx-zcu102, xlnx-versal-virt: Support BBRAM and eFUSE devices * gdbstub related code cleanups * Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML * Use _init vs _new convention in bus creation function names * sabrelite: Connect SPI flash CS line to GPIO3_19
# gpg: Signature made Thu 30 Sep 2021 16:11:20 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210930: (22 commits) hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19 ide: Rename ide_bus_new() to ide_bus_init() qbus: Rename qbus_create() to qbus_new() qbus: Rename qbus_create_inplace() to qbus_init() pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init() ipack: Rename ipack_bus_new_inplace() to ipack_bus_init() scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named() target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML target/arm: Move gdbstub related code out of helper.c target/arm: Fix coding style issues in gdbstub code in helper.c configs: Don't include 32-bit-only GDB XML in aarch64 linux configs docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage hw/arm: xlnx-zcu102: Add Xilinx eFUSE device hw/arm: xlnx-zcu102: Add Xilinx BBRAM device hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device hw/nvram: Introduce Xilinx battery-backed ram hw/nvram: Introduce Xilinx ZynqMP eFuse device hw/nvram: Introduce Xilinx Versal eFuse device hw/nvram: Introduce Xilinx eFuse QOM ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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d637e1dc |
| 23-Sep-2021 |
Peter Maydell <peter.maydell@linaro.org> |
qbus: Rename qbus_create_inplace() to qbus_init()
Rename qbus_create_inplace() to qbus_init(); this is more in line with our usual naming convention for functions that in-place initialize objects.
qbus: Rename qbus_create_inplace() to qbus_init()
Rename qbus_create_inplace() to qbus_init(); this is more in line with our usual naming convention for functions that in-place initialize objects.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20210923121153.23754-5-peter.maydell@linaro.org
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Revision tags: v6.1.0 |
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0bcd12fb |
| 28-Jan-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
Block layer patches:
- Fix crash on write to read-only devices - iotests: Rewrite 'check' in Python, get rid of 'groups'
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
Block layer patches:
- Fix crash on write to read-only devices - iotests: Rewrite 'check' in Python, get rid of 'groups' and allow non-numeric test case names
# gpg: Signature made Wed 27 Jan 2021 19:56:00 GMT # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6
* remotes/kevin/tags/for-upstream: iotests: rename and move 169 and 199 tests iotests: rewrite check into python iotests: add testrunner.py iotests: add testenv.py iotests: add findtests.py iotests: 146: drop extra whitespaces from .out file virtio-scsi-test: Test writing to scsi-cd device block: Separate blk_is_writable() and blk_supports_write_perm()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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86b1cf32 |
| 18-Jan-2021 |
Kevin Wolf <kwolf@redhat.com> |
block: Separate blk_is_writable() and blk_supports_write_perm()
Currently, blk_is_read_only() tells whether a given BlockBackend can only be used in read-only mode because its root node is read-only
block: Separate blk_is_writable() and blk_supports_write_perm()
Currently, blk_is_read_only() tells whether a given BlockBackend can only be used in read-only mode because its root node is read-only. Some callers actually try to answer a slightly different question: Is the BlockBackend configured to be writable, by taking write permissions on the root node?
This can differ, for example, for CD-ROM devices which don't take write permissions, but may be backed by a writable image file. scsi-cd allows write requests to the drive if blk_is_read_only() returns false. However, the write request will immediately run into an assertion failure because the write permission is missing.
This patch introduces separate functions for both questions. blk_supports_write_perm() answers the question whether the block node/image file can support writable devices, whereas blk_is_writable() tells whether the BlockBackend is currently configured to be writable.
All calls of blk_is_read_only() are converted to one of the two new functions.
Fixes: https://bugs.launchpad.net/bugs/1906693 Cc: qemu-stable@nongnu.org Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20210118123448.307825-2-kwolf@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
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Revision tags: v5.2.0 |
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3e39dac0 |
| 28-Aug-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
Machine queue + QOM fixes and cleanups
Bug fix: * numa: hmat: fix cache size check (Igor Mammedov)
QOM f
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
Machine queue + QOM fixes and cleanups
Bug fix: * numa: hmat: fix cache size check (Igor Mammedov)
QOM fixes and cleanups: * Move QOM macros and typedefs to header files * Use TYPE_* constants on TypeInfo structs * Rename QOM type checking macros for consistency * Rename enum values and typedefs that conflict with QOM type checking amcros * Fix typos on QOM type checking macros * Delete unused QOM type checking macros that use non-existing typedefs * hvf: Add missing include * xen-legacy-backend: Add missing typedef XenLegacyDevice
# gpg: Signature made Thu 27 Aug 2020 20:20:05 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6
* remotes/ehabkost/tags/machine-next-pull-request: (53 commits) dc390: Use TYPE_DC390_DEVICE constant ppce500: Use TYPE_PPC_E500_PCI_BRIDGE constant tosa: Use TYPE_TOSA_MISC_GPIO constant xlnx-zcu102: Use TYPE_ZCU102_MACHINE constant sclpconsole: Use TYPE_* constants amd_iommu: Use TYPE_AMD_IOMMU_PCI constant nios2_iic: Use TYPE_ALTERA_IIC constant etsec: Use TYPE_ETSEC_COMMON constant migration: Rename class type checking macros swim: Rename struct SWIM to Swim s390-virtio-ccw: Rename S390_MACHINE_CLASS macro nubus: Rename class type checking macros vfio/pci: Move QOM macros to header kvm: Move QOM macros to kvm.h mptsas: Move QOM macros to header pxa2xx: Move QOM macros to header rocker: Move QOM macros to header auxbus: Move QOM macros to header piix: Move QOM macros to header virtio-serial-bus: Move QOM macros to header ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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b694ed1f |
| 25-Aug-2020 |
Eduardo Habkost <ehabkost@redhat.com> |
swim: Rename struct SWIM to Swim
Currently we have a SWIM typedef and a SWIM type checking macro, but OBJECT_DECLARE* would transform the SWIM macro into a function, and the function name would conf
swim: Rename struct SWIM to Swim
Currently we have a SWIM typedef and a SWIM type checking macro, but OBJECT_DECLARE* would transform the SWIM macro into a function, and the function name would conflict with the SWIM typedef name.
Rename the struct and typedef to "Swim". This will make future conversion to OBJECT_DECLARE* easier.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Laurent Vivier <laurent@vivier.eu> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-50-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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3b268766 |
| 18-Jun-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
Block layer patches:
- enhance handling of size-related BlockConf properties - nvme: small fixes, refactoring and cleanup
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
Block layer patches:
- enhance handling of size-related BlockConf properties - nvme: small fixes, refactoring and cleanups - virtio-blk: On restart, process queued requests in the proper context - icount: make dma reads deterministic - iotests: Some fixes for rarely run cases - .gitignore: Ignore storage-daemon files - Minor code cleanups
# gpg: Signature made Wed 17 Jun 2020 15:47:19 BST # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6
* remotes/kevin/tags/for-upstream: (43 commits) iotests: Add copyright line in qcow2.py iotests/{190,291}: compat=0.10 is unsupported iotests/229: data_file is unsupported iotests/292: data_file is unsupported iotests/041: Skip test_small_target for qed iotests.py: Add skip_for_formats() decorator block: lift blocksize property limit to 2 MiB qdev-properties: add getter for size32 and blocksize block: make BlockConf size props 32bit and accept size suffixes qdev-properties: make blocksize accept size suffixes qdev-properties: add size32 property type qdev-properties: blocksize: use same limits in code and description block: consolidate blocksize properties consistency checks virtio-blk: store opt_io_size with correct size .gitignore: Ignore storage-daemon files hw/block/nvme: verify msix_init_exclusive_bar() return value hw/block/nvme: add msix_qsize parameter hw/block/nvme: Verify msix_vector_use() returned value hw/block/nvme: factor out controller identify setup hw/block/nvme: do cmb/pmr init as part of pci init ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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c56ee92f |
| 28-May-2020 |
Roman Kagan <rvkagan@yandex-team.ru> |
block: consolidate blocksize properties consistency checks
Several block device properties related to blocksize configuration must be in certain relationship WRT each other: physical block must be n
block: consolidate blocksize properties consistency checks
Several block device properties related to blocksize configuration must be in certain relationship WRT each other: physical block must be no smaller than logical block; min_io_size, opt_io_size, and discard_granularity must be a multiple of a logical block.
To ensure these requirements are met, add corresponding consistency checks to blkconf_blocksizes, adjusting its signature to communicate possible error to the caller. Also remove the now redundant consistency checks from the specific devices.
Signed-off-by: Roman Kagan <rvkagan@yandex-team.ru> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Paul Durrant <paul@xen.org> Message-Id: <20200528225516.1676602-3-rvkagan@yandex-team.ru> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
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Revision tags: v5.0.0 |
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760df0d1 |
| 27-Jan-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
* Register qdev properties as class properties (Marc-André) * Cleanups (Philippe) * virtio-scsi fix (Pan Nengyuan) * Twe
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
* Register qdev properties as class properties (Marc-André) * Cleanups (Philippe) * virtio-scsi fix (Pan Nengyuan) * Tweak Skylake-v3 model id (Kashyap) * x86 UCODE_REV support and nested live migration fix (myself) * Advisory mode for pvpanic (Zhenwei)
# gpg: Signature made Fri 24 Jan 2020 20:16:23 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini/tags/for-upstream: (58 commits) build-sys: clean up flags included in the linker command line target/i386: Add the 'model-id' for Skylake -v3 CPU models qdev: use object_property_help() qapi/qmp: add ObjectPropertyInfo.default-value qom: introduce object_property_help() qom: simplify qmp_device_list_properties() vl: print default value in object help qdev: register properties as class properties qdev: move instance properties to class properties qdev: rename DeviceClass.props qdev: set properties with device_class_set_props() object: return self in object_ref() object: release all props object: add object_class_property_add_link() object: express const link with link property object: add direct link flag object: rename link "child" to "target" object: check strong flag with & object: do not free class properties object: add object_property_set_default ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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4f67d30b |
| 10-Jan-2020 |
Marc-André Lureau <marcandre.lureau@redhat.com> |
qdev: set properties with device_class_set_props()
The following patch will need to handle properties registration during class_init time. Let's use a device_class_set_props() setter.
spatch --macr
qdev: set properties with device_class_set_props()
The following patch will need to handle properties registration during class_init time. Let's use a device_class_set_props() setter.
spatch --macro-file scripts/cocci-macro-file.h --sp-file ./scripts/coccinelle/qdev-set-props.cocci --keep-comments --in-place --dir .
@@ typedef DeviceClass; DeviceClass *d; expression val; @@ - d->props = val + device_class_set_props(d, val)
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200110153039.1379601-20-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v4.2.0 |
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f724de8d |
| 29-Oct-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/vivier/tags/q800-branch-pull-request' into staging
Add Macintosh Quadra 800 machine in hw/m68k
# gpg: Signature made Mon 28 Oct 2019 18:14:25 GMT # gpg:
Merge remote-tracking branch 'remotes/vivier/tags/q800-branch-pull-request' into staging
Add Macintosh Quadra 800 machine in hw/m68k
# gpg: Signature made Mon 28 Oct 2019 18:14:25 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier/tags/q800-branch-pull-request: BootLinuxConsoleTest: Test the Quadra 800 hw/m68k: define Macintosh Quadra 800 hw/m68k: add a dummy SWIM floppy controller hw/m68k: add Nubus macfb video card hw/m68k: add Nubus support hw/m68k: implement ADB bus support for via hw/m68k: add VIA support dp8393x: manage big endian bus esp: add pseudo-DMA as used by Macintosh esp: move get_cmd() post-DMA code to get_cmd_cb() esp: move handle_ti_cmd() cleanup code to esp_do_dma().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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c701ec62 |
| 26-Oct-2019 |
Laurent Vivier <laurent@vivier.eu> |
hw/m68k: add a dummy SWIM floppy controller
SWIM (Sander-Wozniak Integrated Machine) is the floppy controller of the 680x0 Macintosh.
This patch introduces only the basic support: it allows to swit
hw/m68k: add a dummy SWIM floppy controller
SWIM (Sander-Wozniak Integrated Machine) is the floppy controller of the 680x0 Macintosh.
This patch introduces only the basic support: it allows to switch from IWM (Integrated WOZ Machine) mode to the SWIM mode and makes the linux driver happy.
It cannot read any floppy image.
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20191026164546.30020-10-laurent@vivier.eu>
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