1*22af900bSThierry Reding# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*22af900bSThierry Reding%YAML 1.2 3*22af900bSThierry Reding--- 4*22af900bSThierry Reding$id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml# 5*22af900bSThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml# 6*22af900bSThierry Reding 7*22af900bSThierry Redingtitle: NVIDIA Tegra124 SOCTHERM Thermal Management System 8*22af900bSThierry Reding 9*22af900bSThierry Redingmaintainers: 10*22af900bSThierry Reding - Thierry Reding <thierry.reding@gmail.com> 11*22af900bSThierry Reding - Jon Hunter <jonathanh@nvidia.com> 12*22af900bSThierry Reding 13*22af900bSThierry Redingdescription: The SOCTHERM IP block contains thermal sensors, support for 14*22af900bSThierry Reding polled or interrupt-based thermal monitoring, CPU and GPU throttling based 15*22af900bSThierry Reding on temperature trip points, and handling external overcurrent notifications. 16*22af900bSThierry Reding It is also used to manage emergency shutdown in an overheating situation. 17*22af900bSThierry Reding 18*22af900bSThierry Redingproperties: 19*22af900bSThierry Reding compatible: 20*22af900bSThierry Reding enum: 21*22af900bSThierry Reding - nvidia,tegra124-soctherm 22*22af900bSThierry Reding - nvidia,tegra132-soctherm 23*22af900bSThierry Reding - nvidia,tegra210-soctherm 24*22af900bSThierry Reding 25*22af900bSThierry Reding reg: 26*22af900bSThierry Reding maxItems: 2 27*22af900bSThierry Reding 28*22af900bSThierry Reding reg-names: 29*22af900bSThierry Reding maxItems: 2 30*22af900bSThierry Reding 31*22af900bSThierry Reding interrupts: 32*22af900bSThierry Reding items: 33*22af900bSThierry Reding - description: module interrupt 34*22af900bSThierry Reding - description: EDP interrupt 35*22af900bSThierry Reding 36*22af900bSThierry Reding interrupt-names: 37*22af900bSThierry Reding items: 38*22af900bSThierry Reding - const: thermal 39*22af900bSThierry Reding - const: edp 40*22af900bSThierry Reding 41*22af900bSThierry Reding clocks: 42*22af900bSThierry Reding items: 43*22af900bSThierry Reding - description: thermal sensor clock 44*22af900bSThierry Reding - description: module clock 45*22af900bSThierry Reding 46*22af900bSThierry Reding clock-names: 47*22af900bSThierry Reding items: 48*22af900bSThierry Reding - const: tsensor 49*22af900bSThierry Reding - const: soctherm 50*22af900bSThierry Reding 51*22af900bSThierry Reding resets: 52*22af900bSThierry Reding items: 53*22af900bSThierry Reding - description: module reset 54*22af900bSThierry Reding 55*22af900bSThierry Reding reset-names: 56*22af900bSThierry Reding items: 57*22af900bSThierry Reding - const: soctherm 58*22af900bSThierry Reding 59*22af900bSThierry Reding "#thermal-sensor-cells": 60*22af900bSThierry Reding const: 1 61*22af900bSThierry Reding 62*22af900bSThierry Reding throttle-cfgs: 63*22af900bSThierry Reding $ref: thermal-cooling-devices.yaml 64*22af900bSThierry Reding description: A sub-node which is a container of configuration for each 65*22af900bSThierry Reding hardware throttle events. These events can be set as cooling devices. 66*22af900bSThierry Reding Throttle event sub-nodes must be named as "light" or "heavy". 67*22af900bSThierry Reding unevaluatedProperties: false 68*22af900bSThierry Reding patternProperties: 69*22af900bSThierry Reding "^(light|heavy|oc1)$": 70*22af900bSThierry Reding type: object 71*22af900bSThierry Reding properties: 72*22af900bSThierry Reding nvidia,priority: 73*22af900bSThierry Reding $ref: /schemas/types.yaml#/definitions/uint32 74*22af900bSThierry Reding minimum: 1 75*22af900bSThierry Reding maximum: 100 76*22af900bSThierry Reding description: Each throttles has its own throttle settings, so the 77*22af900bSThierry Reding SW need to set priorities for various throttle, the HW arbiter 78*22af900bSThierry Reding can select the final throttle settings. Bigger value indicates 79*22af900bSThierry Reding higher priority, In general, higher priority translates to lower 80*22af900bSThierry Reding target frequency. SW needs to ensure that critical thermal 81*22af900bSThierry Reding alarms are given higher priority, and ensure that there is no 82*22af900bSThierry Reding race if priority of two vectors is set to the same value. 83*22af900bSThierry Reding 84*22af900bSThierry Reding nvidia,cpu-throt-percent: 85*22af900bSThierry Reding description: This property is for Tegra124 and Tegra210. It is the 86*22af900bSThierry Reding throttling depth of pulse skippers, it's the percentage 87*22af900bSThierry Reding throttling. 88*22af900bSThierry Reding minimum: 0 89*22af900bSThierry Reding maximum: 100 90*22af900bSThierry Reding 91*22af900bSThierry Reding nvidia,cpu-throt-level: 92*22af900bSThierry Reding $ref: /schemas/types.yaml#/definitions/uint32 93*22af900bSThierry Reding description: This property is only for Tegra132, it is the level 94*22af900bSThierry Reding of pulse skippers, which used to throttle clock frequencies. It 95*22af900bSThierry Reding indicates cpu clock throttling depth, and the depth can be 96*22af900bSThierry Reding programmed. 97*22af900bSThierry Reding enum: 98*22af900bSThierry Reding # none (TEGRA_SOCTHERM_THROT_LEVEL_NONE) 99*22af900bSThierry Reding - 0 100*22af900bSThierry Reding # low (TEGRA_SOCTHERM_THROT_LEVEL_LOW) 101*22af900bSThierry Reding - 1 102*22af900bSThierry Reding # medium (TEGRA_SOCTHERM_THROT_LEVEL_MED) 103*22af900bSThierry Reding - 2 104*22af900bSThierry Reding # high (TEGRA_SOCTHERM_THROT_LEVEL_HIGH) 105*22af900bSThierry Reding - 3 106*22af900bSThierry Reding 107*22af900bSThierry Reding nvidia,gpu-throt-level: 108*22af900bSThierry Reding $ref: /schemas/types.yaml#/definitions/uint32 109*22af900bSThierry Reding description: This property is for Tegra124 and Tegra210. It is the 110*22af900bSThierry Reding level of pulse skippers, which used to throttle clock 111*22af900bSThierry Reding frequencies. It indicates gpu clock throttling depth and can be 112*22af900bSThierry Reding programmed to any of the following values which represent a 113*22af900bSThierry Reding throttling percentage. 114*22af900bSThierry Reding enum: 115*22af900bSThierry Reding # none (0%, TEGRA_SOCTHERM_THROT_LEVEL_NONE) 116*22af900bSThierry Reding - 0 117*22af900bSThierry Reding # low (50%, TEGRA_SOCTHERM_THROT_LEVEL_LOW) 118*22af900bSThierry Reding - 1 119*22af900bSThierry Reding # medium (75%, TEGRA_SOCTHERM_THROT_LEVEL_MED) 120*22af900bSThierry Reding - 2 121*22af900bSThierry Reding # high (85%, TEGRA_SOCTHERM_THROT_LEVEL_HIGH) 122*22af900bSThierry Reding - 3 123*22af900bSThierry Reding 124*22af900bSThierry Reding # optional 125*22af900bSThierry Reding # Tegra210 specific and valid only for OCx throttle events 126*22af900bSThierry Reding nvidia,count-threshold: 127*22af900bSThierry Reding $ref: /schemas/types.yaml#/definitions/uint32 128*22af900bSThierry Reding description: Specifies the number of OC events that are required 129*22af900bSThierry Reding for triggering an interrupt. Interrupts are not triggered if the 130*22af900bSThierry Reding property is missing. A value of 0 will interrupt on every OC 131*22af900bSThierry Reding alarm. 132*22af900bSThierry Reding 133*22af900bSThierry Reding nvidia,polarity-active-low: 134*22af900bSThierry Reding $ref: /schemas/types.yaml#/definitions/flag 135*22af900bSThierry Reding description: Configures the polarity of the OC alaram signal. If 136*22af900bSThierry Reding present, this means assert low, otherwise assert high. 137*22af900bSThierry Reding 138*22af900bSThierry Reding nvidia,alarm-filter: 139*22af900bSThierry Reding $ref: /schemas/types.yaml#/definitions/uint32 140*22af900bSThierry Reding description: Number of clocks to filter event. When the filter 141*22af900bSThierry Reding expires (which means the OC event has not occurred for a long 142*22af900bSThierry Reding time), the counter is cleared and filter is rearmed. 143*22af900bSThierry Reding default: 0 144*22af900bSThierry Reding 145*22af900bSThierry Reding nvidia,throttle-period-us: 146*22af900bSThierry Reding description: Specifies the number of microseconds for which 147*22af900bSThierry Reding throttling is engaged after the OC event is deasserted. 148*22af900bSThierry Reding default: 0 149*22af900bSThierry Reding 150*22af900bSThierry Reding # optional 151*22af900bSThierry Reding nvidia,thermtrips: 152*22af900bSThierry Reding $ref: /schemas/types.yaml#/definitions/uint32-matrix 153*22af900bSThierry Reding description: | 154*22af900bSThierry Reding When present, this property specifies the temperature at which the 155*22af900bSThierry Reding SOCTHERM hardware will assert the thermal trigger signal to the Power 156*22af900bSThierry Reding Management IC, which can be configured to reset or shutdown the device. 157*22af900bSThierry Reding It is an array of pairs where each pair represents a tsensor ID followed 158*22af900bSThierry Reding by a temperature in milli Celcius. In the absence of this property the 159*22af900bSThierry Reding critical trip point will be used for thermtrip temperature. 160*22af900bSThierry Reding 161*22af900bSThierry Reding Note: 162*22af900bSThierry Reding - the "critical" type trip points will be used to set the temperature at 163*22af900bSThierry Reding which the SOCTHERM hardware will assert a thermal trigger if the 164*22af900bSThierry Reding "nvidia,thermtrips" property is missing. When the thermtrips property 165*22af900bSThierry Reding is present, the breach of a critical trip point is reported back to 166*22af900bSThierry Reding the thermal framework to implement software shutdown. 167*22af900bSThierry Reding 168*22af900bSThierry Reding - the "hot" type trip points will be set to SOCTHERM hardware as the 169*22af900bSThierry Reding throttle temperature. Once the temperature of this thermal zone is 170*22af900bSThierry Reding higher than it, it will trigger the HW throttle event. 171*22af900bSThierry Reding items: 172*22af900bSThierry Reding items: 173*22af900bSThierry Reding - description: sensor ID 174*22af900bSThierry Reding oneOf: 175*22af900bSThierry Reding - description: CPU sensor 176*22af900bSThierry Reding const: 0 177*22af900bSThierry Reding - description: MEM sensor 178*22af900bSThierry Reding const: 1 179*22af900bSThierry Reding - description: GPU sensor 180*22af900bSThierry Reding const: 2 181*22af900bSThierry Reding - description: PLLX sensor 182*22af900bSThierry Reding const: 3 183*22af900bSThierry Reding - description: temperature threshold (in millidegree Celsius) 184*22af900bSThierry Reding 185*22af900bSThierry Redingrequired: 186*22af900bSThierry Reding - compatible 187*22af900bSThierry Reding - reg 188*22af900bSThierry Reding - reg-names 189*22af900bSThierry Reding - interrupts 190*22af900bSThierry Reding - interrupt-names 191*22af900bSThierry Reding - clocks 192*22af900bSThierry Reding - clock-names 193*22af900bSThierry Reding - resets 194*22af900bSThierry Reding - reset-names 195*22af900bSThierry Reding - "#thermal-sensor-cells" 196*22af900bSThierry Reding 197*22af900bSThierry RedingallOf: 198*22af900bSThierry Reding - $ref: thermal-sensor.yaml 199*22af900bSThierry Reding - if: 200*22af900bSThierry Reding properties: 201*22af900bSThierry Reding compatible: 202*22af900bSThierry Reding contains: 203*22af900bSThierry Reding enum: 204*22af900bSThierry Reding - nvidia,tegra124-soctherm 205*22af900bSThierry Reding - nvidia,tegra210-soctherm 206*22af900bSThierry Reding then: 207*22af900bSThierry Reding properties: 208*22af900bSThierry Reding reg: 209*22af900bSThierry Reding items: 210*22af900bSThierry Reding - description: SOCTHERM register set 211*22af900bSThierry Reding - description: clock and reset controller registers 212*22af900bSThierry Reding 213*22af900bSThierry Reding reg-names: 214*22af900bSThierry Reding items: 215*22af900bSThierry Reding - const: soctherm-reg 216*22af900bSThierry Reding - const: car-reg 217*22af900bSThierry Reding 218*22af900bSThierry Reding else: 219*22af900bSThierry Reding properties: 220*22af900bSThierry Reding reg: 221*22af900bSThierry Reding items: 222*22af900bSThierry Reding - description: SOCTHERM register set 223*22af900bSThierry Reding - description: CCROC registers 224*22af900bSThierry Reding 225*22af900bSThierry Reding reg-names: 226*22af900bSThierry Reding items: 227*22af900bSThierry Reding - const: soctherm-reg 228*22af900bSThierry Reding - const: ccroc-reg 229*22af900bSThierry Reding 230*22af900bSThierry RedingadditionalProperties: false 231*22af900bSThierry Reding 232*22af900bSThierry Redingexamples: 233*22af900bSThierry Reding - | 234*22af900bSThierry Reding #include <dt-bindings/clock/tegra124-car.h> 235*22af900bSThierry Reding #include <dt-bindings/interrupt-controller/arm-gic.h> 236*22af900bSThierry Reding #include <dt-bindings/thermal/tegra124-soctherm.h> 237*22af900bSThierry Reding 238*22af900bSThierry Reding soctherm@700e2000 { 239*22af900bSThierry Reding compatible = "nvidia,tegra124-soctherm"; 240*22af900bSThierry Reding reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */ 241*22af900bSThierry Reding <0x60006000 0x400>; /* CAR reg_base */ 242*22af900bSThierry Reding reg-names = "soctherm-reg", "car-reg"; 243*22af900bSThierry Reding interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 244*22af900bSThierry Reding <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 245*22af900bSThierry Reding interrupt-names = "thermal", "edp"; 246*22af900bSThierry Reding clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 247*22af900bSThierry Reding <&tegra_car TEGRA124_CLK_SOC_THERM>; 248*22af900bSThierry Reding clock-names = "tsensor", "soctherm"; 249*22af900bSThierry Reding resets = <&tegra_car 78>; 250*22af900bSThierry Reding reset-names = "soctherm"; 251*22af900bSThierry Reding 252*22af900bSThierry Reding #thermal-sensor-cells = <1>; 253*22af900bSThierry Reding 254*22af900bSThierry Reding nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500>, 255*22af900bSThierry Reding <TEGRA124_SOCTHERM_SENSOR_GPU 103000>; 256*22af900bSThierry Reding 257*22af900bSThierry Reding throttle-cfgs { 258*22af900bSThierry Reding /* 259*22af900bSThierry Reding * When the "heavy" cooling device triggered, 260*22af900bSThierry Reding * the HW will skip cpu clock's pulse in 85% depth, 261*22af900bSThierry Reding * skip gpu clock's pulse in 85% level 262*22af900bSThierry Reding */ 263*22af900bSThierry Reding heavy { 264*22af900bSThierry Reding nvidia,priority = <100>; 265*22af900bSThierry Reding nvidia,cpu-throt-percent = <85>; 266*22af900bSThierry Reding nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 267*22af900bSThierry Reding 268*22af900bSThierry Reding #cooling-cells = <2>; 269*22af900bSThierry Reding }; 270*22af900bSThierry Reding 271*22af900bSThierry Reding /* 272*22af900bSThierry Reding * When the "light" cooling device triggered, 273*22af900bSThierry Reding * the HW will skip cpu clock's pulse in 50% depth, 274*22af900bSThierry Reding * skip gpu clock's pulse in 50% level 275*22af900bSThierry Reding */ 276*22af900bSThierry Reding light { 277*22af900bSThierry Reding nvidia,priority = <80>; 278*22af900bSThierry Reding nvidia,cpu-throt-percent = <50>; 279*22af900bSThierry Reding nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>; 280*22af900bSThierry Reding 281*22af900bSThierry Reding #cooling-cells = <2>; 282*22af900bSThierry Reding }; 283*22af900bSThierry Reding 284*22af900bSThierry Reding /* 285*22af900bSThierry Reding * If these two devices are triggered in same time, the HW throttle 286*22af900bSThierry Reding * arbiter will select the highest priority as the final throttle 287*22af900bSThierry Reding * settings to skip cpu pulse. 288*22af900bSThierry Reding */ 289*22af900bSThierry Reding 290*22af900bSThierry Reding oc1 { 291*22af900bSThierry Reding nvidia,priority = <50>; 292*22af900bSThierry Reding nvidia,polarity-active-low; 293*22af900bSThierry Reding nvidia,count-threshold = <100>; 294*22af900bSThierry Reding nvidia,alarm-filter = <5100000>; 295*22af900bSThierry Reding nvidia,throttle-period-us = <0>; 296*22af900bSThierry Reding nvidia,cpu-throt-percent = <75>; 297*22af900bSThierry Reding nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>; 298*22af900bSThierry Reding }; 299*22af900bSThierry Reding }; 300*22af900bSThierry Reding }; 301*22af900bSThierry Reding 302*22af900bSThierry Reding # referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" 303*22af900bSThierry Reding - | 304*22af900bSThierry Reding thermal-sensor@700e2000 { 305*22af900bSThierry Reding compatible = "nvidia,tegra132-soctherm"; 306*22af900bSThierry Reding reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */ 307*22af900bSThierry Reding <0x70040000 0x200>; /* CCROC reg_base */ 308*22af900bSThierry Reding reg-names = "soctherm-reg", "ccroc-reg"; 309*22af900bSThierry Reding interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 310*22af900bSThierry Reding <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 311*22af900bSThierry Reding interrupt-names = "thermal", "edp"; 312*22af900bSThierry Reding clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 313*22af900bSThierry Reding <&tegra_car TEGRA124_CLK_SOC_THERM>; 314*22af900bSThierry Reding clock-names = "tsensor", "soctherm"; 315*22af900bSThierry Reding resets = <&tegra_car 78>; 316*22af900bSThierry Reding reset-names = "soctherm"; 317*22af900bSThierry Reding #thermal-sensor-cells = <1>; 318*22af900bSThierry Reding 319*22af900bSThierry Reding throttle-cfgs { 320*22af900bSThierry Reding /* 321*22af900bSThierry Reding * When the "heavy" cooling device triggered, 322*22af900bSThierry Reding * the HW will skip cpu clock's pulse in HIGH level 323*22af900bSThierry Reding */ 324*22af900bSThierry Reding heavy { 325*22af900bSThierry Reding nvidia,priority = <100>; 326*22af900bSThierry Reding nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 327*22af900bSThierry Reding 328*22af900bSThierry Reding #cooling-cells = <2>; 329*22af900bSThierry Reding }; 330*22af900bSThierry Reding 331*22af900bSThierry Reding /* 332*22af900bSThierry Reding * When the "light" cooling device triggered, 333*22af900bSThierry Reding * the HW will skip cpu clock's pulse in MED level 334*22af900bSThierry Reding */ 335*22af900bSThierry Reding light { 336*22af900bSThierry Reding nvidia,priority = <80>; 337*22af900bSThierry Reding nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>; 338*22af900bSThierry Reding 339*22af900bSThierry Reding #cooling-cells = <2>; 340*22af900bSThierry Reding }; 341*22af900bSThierry Reding 342*22af900bSThierry Reding /* 343*22af900bSThierry Reding * If these two devices are triggered in same time, the HW throttle 344*22af900bSThierry Reding * arbiter will select the highest priority as the final throttle 345*22af900bSThierry Reding * settings to skip cpu pulse. 346*22af900bSThierry Reding */ 347*22af900bSThierry Reding }; 348*22af900bSThierry Reding }; 349*22af900bSThierry Reding 350*22af900bSThierry Reding # referring to thermal sensors 351*22af900bSThierry Reding - | 352*22af900bSThierry Reding thermal-zones { 353*22af900bSThierry Reding cpu-thermal { 354*22af900bSThierry Reding polling-delay-passive = <1000>; 355*22af900bSThierry Reding polling-delay = <1000>; 356*22af900bSThierry Reding 357*22af900bSThierry Reding thermal-sensors = <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 358*22af900bSThierry Reding 359*22af900bSThierry Reding trips { 360*22af900bSThierry Reding cpu_shutdown_trip: shutdown-trip { 361*22af900bSThierry Reding temperature = <102500>; 362*22af900bSThierry Reding hysteresis = <1000>; 363*22af900bSThierry Reding type = "critical"; 364*22af900bSThierry Reding }; 365*22af900bSThierry Reding 366*22af900bSThierry Reding cpu_throttle_trip: throttle-trip { 367*22af900bSThierry Reding temperature = <100000>; 368*22af900bSThierry Reding hysteresis = <1000>; 369*22af900bSThierry Reding type = "hot"; 370*22af900bSThierry Reding }; 371*22af900bSThierry Reding }; 372*22af900bSThierry Reding 373*22af900bSThierry Reding cooling-maps { 374*22af900bSThierry Reding map0 { 375*22af900bSThierry Reding trip = <&cpu_throttle_trip>; 376*22af900bSThierry Reding cooling-device = <&throttle_heavy 1 1>; 377*22af900bSThierry Reding }; 378*22af900bSThierry Reding }; 379*22af900bSThierry Reding }; 380*22af900bSThierry Reding }; 381