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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dmarvell,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell NAND Flash Controller (NFC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 - items:
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
18 - enum:
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A DKconfig2 menuconfig NAND config
3 bool "Raw NAND Device Support"
4 if NAND
6 config SYS_NAND_SELF_INIT
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
12 config SYS_NAND_DRIVER_ECC_LAYOUT
18 config NAND_ATMEL
19 bool "Support Atmel NAND controller"
22 Enable this driver for NAND flash platforms using an Atmel NAND
[all …]
H A Dpxa3xx_nand.h23 struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
32 * keep configuration feature, for two chip select could be
33 * attached with different nand chip. The different page size
34 * and timing requirement make the keep configuration impossible.
46 /* allow platform code to keep OBM/bootloader defined NFC config */
52 /* use an flash-based bad block table */
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Du-boot-nand_spl.lds1 /* SPDX-License-Identifier: GPL-2.0+ */
9 #include "config.h"
22 KEEP(*(.got2))
23 KEEP(*(.got))
25 KEEP(*(.fixup))
27 __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
28 __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
39 KEEP(*(SORT(.u_boot_list*)));
55 #error unknown NAND controller
58 KEEP(*(.resetvec))
[all …]
H A Du-boot-spl.lds1 /* SPDX-License-Identifier: GPL-2.0+ */
9 #include "config.h"
29 KEEP(*(.got2))
30 KEEP(*(.got))
32 KEEP(*(.fixup))
34 __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
35 __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
47 KEEP(*(SORT(.u_boot_list*)));
72 .bootpg ADDR(.text) - 0x1000 :
74 KEEP(*(.bootpg))
[all …]
/openbmc/u-boot/doc/
H A DREADME.at914 - I. Board mapping & boot media
5 - II. NAND partition table
6 - III. watchdog support
9 ------------------------------------------------------------------------------
11 ------------------------------------------------------------------------------
14 0x20000000 - 23FFFFFF SDRAM (64 MB)
15 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J13)
16 0xD0000000 - D07FFFFF Soldered Atmel Dataflash (AT45DB642)
20 U-Boot environment variables can be stored at different places:
21 - Dataflash on SPI chip select 1 (default)
[all …]
H A DREADME.ramboot-ppc85xx5 pre-mechanism is required to load the DDR with the bootloader binary.
6 - In case of SD and SPI boot this is done by BootROM code inside the chip
8 - In case of NAND boot FCM supports loading initial 4K code from NAND flash
18 - In very early stage of platform bringup where other boot options are not
20 - In case the support to program the flashes on the board is not available.
25 - While developing some new feature of u-boot, for example USB driver or
28 prefer to keep it intact, at the same time want to test your bootloader.
31 - Suppose a platform already has a propreitery bootloader which does not
39 bootloader or for that matter even NAND bootloader.
41 The main difference among all of them is the way the pre-environment is getting
[all …]
H A DREADME.mpc85xx2 ----------------------
7 - MSR[DE] must be set
8 - A valid opcode must be fetchable, through the MMU, from the debug
11 To maximize the time during which this requirement is met, U-Boot sets MSR[DE]
12 immediately on entry and keeps it set. It also uses a temporary TLB to keep a
15 where U-Boot currently executes from.
20 Config Switches:
21 ----------------
25 Major Config Switches during various boot Modes
26 ----------------------------------------------
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-370-mirabox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include "armada-370.dtsi"
14 compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
17 stdout-path = "serial0:115200n8";
30 internal-regs {
35 clock-frequency = <600000000>;
40 compatible = "gpio-leds";
[all …]
H A Darmada-395-gp.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 /dts-v1/;
11 #include "armada-395.dtsi"
15 compatible = "marvell,a395-gp", "marvell,armada395",
19 stdout-path = "serial0:115200n8";
31 internal-regs {
34 clock-frequency = <100000>;
62 clock-frequency = <200000000>;
63 broken-cd;
64 wp-inverted;
[all …]
H A Darmada-370-dlink-dns327l.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for D-Link DNS-327L
12 /dts-v1/;
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include "armada-370.dtsi"
19 model = "D-Link DNS-327L";
22 "marvell,armada-370-xp";
25 stdout-path = &uart0;
38 internal-regs {
[all …]
H A Darmada-398-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 /dts-v1/;
11 #include "armada-398.dtsi"
15 compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
18 stdout-path = "serial0:115200n8";
30 internal-regs {
32 pinctrl-0 = <&i2c0_pins>;
33 pinctrl-names = "default";
35 clock-frequency = <100000>;
[all …]
H A Darmada-390-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F6920)
11 /dts-v1/;
12 #include "armada-390.dtsi"
16 compatible = "marvell,a390-db", "marvell,armada390";
19 stdout-path = "serial0:115200n8";
31 internal-regs {
34 clock-frequency = <100000>;
81 pinctrl-0 = <&spi1_pins>;
82 pinctrl-names = "default";
[all …]
H A Darmada-xp-db-xc3-24g4xg.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for DB-XC3-24G4XG board
7 * Based on armada-xp-db.dts
12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 /dts-v1/;
20 #include "armada-xp-98dx3336.dtsi"
23 model = "DB-XC3-24G4XG";
24 compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
37 arm,parity-enable;
38 marvell,ecc-enable;
[all …]
H A Darmada-xp-db-dxbc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for DB-DXBC2 board
7 * Based on armada-xp-db.dts
12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 /dts-v1/;
20 #include "armada-xp-98dx4251.dtsi"
24 compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
43 devbus,bus-width = <16>;
44 devbus,turn-off-ps = <60000>;
45 devbus,badr-skew-ps = <0>;
[all …]
H A Darmada-375-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F6720)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include "armada-375.dtsi"
18 compatible = "marvell,a375-db", "marvell,armada375";
21 stdout-path = "serial0:115200n8";
57 pinctrl-0 = <&spi0_pins>;
[all …]
H A Darmada-370-rd.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (RD-88F6710-A1)
6 * Copied from arch/arm/boot/dts/armada-370-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include <dt-bindings/input/input.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
23 #include <dt-bindings/leds/common.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-370.dtsi"
[all …]
H A Darmada-370-netgear-rn102.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "armada-370.dtsi"
16 compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp";
19 stdout-path = "serial0:115200n8";
32 internal-regs {
45 nr-ports = <1>;
50 pinctrl-0 = <&ge1_rgmii_pins>;
[all …]
H A Darmada-370-netgear-rn104.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "armada-370.dtsi"
16 compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp";
19 stdout-path = "serial0:115200n8";
32 internal-regs {
44 pinctrl-0 = <&ge0_rgmii_pins>;
45 pinctrl-names = "default";
[all …]
H A Darmada-370-seagate-nas-xbay.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC).
14 #include "armada-370.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
20 stdout-path = "serial0:115200n8";
32 internal-regs {
38 nr-ports = <2>;
44 pinctrl-0 = <&ge0_rgmii_pins>;
45 pinctrl-names = "default";
[all …]
H A Darmada-388-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F6820)
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 /dts-v1/;
12 #include "armada-388.dtsi"
16 compatible = "marvell,a385-db", "marvell,armada388",
20 stdout-path = "serial0:115200n8";
35 internal-regs {
38 clock-frequency = <100000>;
39 audio_codec: audio-codec@4a {
[all …]
/openbmc/u-boot/include/configs/
H A Dx530.h1 /* SPDX-License-Identifier: GPL-2.0+ */
23 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
40 /* NAND */
51 #define MTDIDS_DEFAULT "nand0=nand"
52 #define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)"
76 /* NAND */
87 #include <asm/arch/config.h>
97 /* Keep device tree and initrd in low memory so the kernel can access them */
111 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
120 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt4 different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
[all …]
/openbmc/linux/drivers/clk/st/
H A Dclk-flexgen.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-flexgen.c
5 * Copyright (C) ST-Microelectronics SA 2013
6 * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
10 #include <linux/clk-provider.h>
36 /* Pre-divisor's gate */
38 /* Pre-divisor */
56 struct clk_hw *pgate_hw = &flexgen->pgate.hw; in flexgen_enable()
57 struct clk_hw *fgate_hw = &flexgen->fgate.hw; in flexgen_enable()
73 struct clk_hw *fgate_hw = &flexgen->fgate.hw; in flexgen_disable()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-375-db.dts3 * (DB-88F6720)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
49 /dts-v1/;
50 #include <dt-bindings/gpio/gpio.h>
51 #include "armada-375.dtsi"
55 compatible = "marvell,a375-db", "marvell,armada375";
58 stdout-path = "serial0:115200n8";
62 /* So that mvebu u-boot can update the MAC addresses */
[all …]

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