183d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0+ */ 2a47a12beSStefan Roese/* 3a47a12beSStefan Roese * (C) Copyright 2006 4a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de 5a47a12beSStefan Roese * 6a47a12beSStefan Roese * Copyright 2009 Freescale Semiconductor, Inc. 7a47a12beSStefan Roese */ 8a47a12beSStefan Roese 96f2ed0e9SMasahiro Yamada#include "config.h" 1052f90dadSDipen Dudhat 11a47a12beSStefan RoeseOUTPUT_ARCH(powerpc) 12a47a12beSStefan RoeseSECTIONS 13a47a12beSStefan Roese{ 14a47a12beSStefan Roese . = 0xfff00000; 15a47a12beSStefan Roese .text : { 1636ae6a8eSHaiying Wang *(.text*) 17a47a12beSStefan Roese } 18a47a12beSStefan Roese _etext = .; 19a47a12beSStefan Roese 20a47a12beSStefan Roese .reloc : { 21a47a12beSStefan Roese _GOT2_TABLE_ = .; 2236ae6a8eSHaiying Wang KEEP(*(.got2)) 23d2a97dafSScott Wood KEEP(*(.got)) 24a47a12beSStefan Roese _FIXUP_TABLE_ = .; 2536ae6a8eSHaiying Wang KEEP(*(.fixup)) 26a47a12beSStefan Roese } 27d2a97dafSScott Wood __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; 28a47a12beSStefan Roese __fixup_entries = (. - _FIXUP_TABLE_) >> 2; 29a47a12beSStefan Roese 30a47a12beSStefan Roese . = ALIGN(8); 31a47a12beSStefan Roese .data : { 32a47a12beSStefan Roese *(.rodata*) 33a47a12beSStefan Roese *(.data*) 34a47a12beSStefan Roese *(.sdata*) 35a47a12beSStefan Roese } 36a47a12beSStefan Roese _edata = .; 37a47a12beSStefan Roese 3855675142SMarek Vasut .u_boot_list : { 39ef123c52SAlbert ARIBAUD KEEP(*(SORT(.u_boot_list*))); 4055675142SMarek Vasut } 4155675142SMarek Vasut 42a47a12beSStefan Roese . = ALIGN(8); 43a47a12beSStefan Roese __init_begin = .; 44a47a12beSStefan Roese __init_end = .; 45*4d3294b1SJagdish Gediya _end = .; 4652f90dadSDipen Dudhat#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ 4752f90dadSDipen Dudhat .bootpg ADDR(.text) + 0x1000 : 4852f90dadSDipen Dudhat { 4952f90dadSDipen Dudhat start.o (.bootpg) 5052f90dadSDipen Dudhat } 5152f90dadSDipen Dudhat#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ 5252f90dadSDipen Dudhat#elif defined(CONFIG_FSL_ELBC) 5352f90dadSDipen Dudhat#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ 5452f90dadSDipen Dudhat#else 5552f90dadSDipen Dudhat#error unknown NAND controller 5652f90dadSDipen Dudhat#endif 5752f90dadSDipen Dudhat .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { 5836ae6a8eSHaiying Wang KEEP(*(.resetvec)) 59a47a12beSStefan Roese } = 0xffff 60a47a12beSStefan Roese 61a47a12beSStefan Roese __bss_start = .; 62a47a12beSStefan Roese .bss : { 6336ae6a8eSHaiying Wang *(.sbss*) 6436ae6a8eSHaiying Wang *(.bss*) 65a47a12beSStefan Roese } 663929fb0aSSimon Glass __bss_end = .; 67a47a12beSStefan Roese} 6852f90dadSDipen DudhatASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big"); 69