1*0e31666dSChris Packham /* SPDX-License-Identifier: GPL-2.0+ */ 2*0e31666dSChris Packham /* 3*0e31666dSChris Packham * Copyright (C) 2018 Allied Telesis Labs 4*0e31666dSChris Packham */ 5*0e31666dSChris Packham 6*0e31666dSChris Packham #ifndef _CONFIG_X530_H 7*0e31666dSChris Packham #define _CONFIG_X530_H 8*0e31666dSChris Packham 9*0e31666dSChris Packham /* 10*0e31666dSChris Packham * High Level Configuration Options (easy to change) 11*0e31666dSChris Packham */ 12*0e31666dSChris Packham 13*0e31666dSChris Packham #define CONFIG_DISPLAY_BOARDINFO_LATE 14*0e31666dSChris Packham 15*0e31666dSChris Packham #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 16*0e31666dSChris Packham 17*0e31666dSChris Packham /* 18*0e31666dSChris Packham * NS16550 Configuration 19*0e31666dSChris Packham */ 20*0e31666dSChris Packham #define CONFIG_SYS_NS16550_SERIAL 21*0e31666dSChris Packham #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 22*0e31666dSChris Packham #if !defined(CONFIG_DM_SERIAL) 23*0e31666dSChris Packham #define CONFIG_SYS_NS16550_REG_SIZE (-4) 24*0e31666dSChris Packham #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE 25*0e31666dSChris Packham #endif 26*0e31666dSChris Packham 27*0e31666dSChris Packham /* 28*0e31666dSChris Packham * Serial Port configuration 29*0e31666dSChris Packham * The following definitions let you select what serial you want to use 30*0e31666dSChris Packham * for your console driver. 31*0e31666dSChris Packham */ 32*0e31666dSChris Packham 33*0e31666dSChris Packham #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 34*0e31666dSChris Packham 35*0e31666dSChris Packham /* 36*0e31666dSChris Packham * Commands configuration 37*0e31666dSChris Packham */ 38*0e31666dSChris Packham #define CONFIG_CMD_PCI 39*0e31666dSChris Packham 40*0e31666dSChris Packham /* NAND */ 41*0e31666dSChris Packham #define CONFIG_SYS_NAND_ONFI_DETECTION 42*0e31666dSChris Packham #define CONFIG_SYS_NAND_USE_FLASH_BBT 43*0e31666dSChris Packham #define CONFIG_SYS_MAX_NAND_DEVICE 1 44*0e31666dSChris Packham 45*0e31666dSChris Packham #define BBT_CUSTOM_SCAN 46*0e31666dSChris Packham #define BBT_CUSTOM_SCAN_PAGE 0 47*0e31666dSChris Packham #define BBT_CUSTOM_SCAN_POSITION 2048 48*0e31666dSChris Packham 49*0e31666dSChris Packham /* SPI NOR flash default params, used by sf commands */ 50*0e31666dSChris Packham 51*0e31666dSChris Packham #define MTDIDS_DEFAULT "nand0=nand" 52*0e31666dSChris Packham #define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)" 53*0e31666dSChris Packham #define MTDPARTS_MTDOOPS "errlog" 54*0e31666dSChris Packham 55*0e31666dSChris Packham /* Partition support */ 56*0e31666dSChris Packham 57*0e31666dSChris Packham /* Additional FS support/configuration */ 58*0e31666dSChris Packham 59*0e31666dSChris Packham /* USB/EHCI configuration */ 60*0e31666dSChris Packham #define CONFIG_EHCI_IS_TDI 61*0e31666dSChris Packham 62*0e31666dSChris Packham /* Environment in SPI NOR flash */ 63*0e31666dSChris Packham #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 64*0e31666dSChris Packham #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 65*0e31666dSChris Packham #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 66*0e31666dSChris Packham #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 67*0e31666dSChris Packham 68*0e31666dSChris Packham #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 69*0e31666dSChris Packham #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 70*0e31666dSChris Packham 71*0e31666dSChris Packham /* PCIe support */ 72*0e31666dSChris Packham #ifndef CONFIG_SPL_BUILD 73*0e31666dSChris Packham #define CONFIG_PCI_SCAN_SHOW 74*0e31666dSChris Packham #endif 75*0e31666dSChris Packham 76*0e31666dSChris Packham /* NAND */ 77*0e31666dSChris Packham #define CONFIG_SYS_NAND_USE_FLASH_BBT 78*0e31666dSChris Packham #define CONFIG_SYS_NAND_ONFI_DETECTION 79*0e31666dSChris Packham #define CONFIG_CMD_UBI 80*0e31666dSChris Packham #define CONFIG_CMD_UBIFS 81*0e31666dSChris Packham #define CONFIG_LZO 82*0e31666dSChris Packham #define CONFIG_MTD_DEVICE 83*0e31666dSChris Packham #define CONFIG_CMD_MTDPARTS 84*0e31666dSChris Packham 85*0e31666dSChris Packham #define CONFIG_SYS_MALLOC_LEN (4 << 20) 86*0e31666dSChris Packham 87*0e31666dSChris Packham #include <asm/arch/config.h> 88*0e31666dSChris Packham 89*0e31666dSChris Packham /* 90*0e31666dSChris Packham * Other required minimal configurations 91*0e31666dSChris Packham */ 92*0e31666dSChris Packham #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 93*0e31666dSChris Packham #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ 94*0e31666dSChris Packham 95*0e31666dSChris Packham #define CONFIG_SYS_ALT_MEMTEST 96*0e31666dSChris Packham 97*0e31666dSChris Packham /* Keep device tree and initrd in low memory so the kernel can access them */ 98*0e31666dSChris Packham #define CONFIG_EXTRA_ENV_SETTINGS \ 99*0e31666dSChris Packham "fdt_high=0x10000000\0" \ 100*0e31666dSChris Packham "initrd_high=0x10000000\0" 101*0e31666dSChris Packham 102*0e31666dSChris Packham #define CONFIG_SYS_LOAD_ADDR 0x1000000 103*0e31666dSChris Packham #define CONFIG_UBI_PART user 104*0e31666dSChris Packham #define CONFIG_UBIFS_VOLUME user 105*0e31666dSChris Packham 106*0e31666dSChris Packham /* SPL */ 107*0e31666dSChris Packham 108*0e31666dSChris Packham /* Defines for SPL */ 109*0e31666dSChris Packham #define CONFIG_SPL_SIZE (140 << 10) 110*0e31666dSChris Packham #define CONFIG_SPL_TEXT_BASE 0x40000030 111*0e31666dSChris Packham #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) 112*0e31666dSChris Packham 113*0e31666dSChris Packham #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) 114*0e31666dSChris Packham #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 115*0e31666dSChris Packham 116*0e31666dSChris Packham #ifdef CONFIG_SPL_BUILD 117*0e31666dSChris Packham #define CONFIG_SYS_MALLOC_SIMPLE 118*0e31666dSChris Packham #endif 119*0e31666dSChris Packham 120*0e31666dSChris Packham #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 121*0e31666dSChris Packham #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 122*0e31666dSChris Packham 123*0e31666dSChris Packham /* SPL related SPI defines */ 124*0e31666dSChris Packham #define CONFIG_SPL_SPI_LOAD 125*0e31666dSChris Packham #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 126*0e31666dSChris Packham #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 127*0e31666dSChris Packham 128*0e31666dSChris Packham #endif /* _CONFIG_X530_H */ 129