156376c42SPoonam Aggrwal RAMBOOT for MPC85xx Platforms 256376c42SPoonam Aggrwal ============================== 356376c42SPoonam Aggrwal 456376c42SPoonam AggrwalRAMBOOT literally means boot from DDR. But since DDR is volatile memory some 556376c42SPoonam Aggrwalpre-mechanism is required to load the DDR with the bootloader binary. 656376c42SPoonam Aggrwal- In case of SD and SPI boot this is done by BootROM code inside the chip 756376c42SPoonam Aggrwal itself. 856376c42SPoonam Aggrwal- In case of NAND boot FCM supports loading initial 4K code from NAND flash 956376c42SPoonam Aggrwal which can initialize the DDR and get the complete bootloader copied to DDR. 1056376c42SPoonam Aggrwal 1156376c42SPoonam AggrwalIn addition to the above there could be some more methods to initialize the DDR 1256376c42SPoonam Aggrwaland load it manually. 1356376c42SPoonam AggrwalTwo of them are described below.There is also an explanation as to where these 1456376c42SPoonam Aggrwalmethods could be handy. 1556376c42SPoonam Aggrwal1. Load the RAM based bootloader onto DDR via JTAG/BDI interface. And then 1656376c42SPoonam Aggrwal execute the bootloader from DDR. 1756376c42SPoonam Aggrwal This may be handy in the following cases: 1856376c42SPoonam Aggrwal - In very early stage of platform bringup where other boot options are not 1956376c42SPoonam Aggrwal functional because of various reasons. 2056376c42SPoonam Aggrwal - In case the support to program the flashes on the board is not available. 2156376c42SPoonam Aggrwal 2256376c42SPoonam Aggrwal2. Load the RAM based bootloader onto DDR using already existing bootloader on 2356376c42SPoonam Aggrwal the board.And then execute the bootloader from DDR. 2456376c42SPoonam Aggrwal Some usecases where this may be used: 2556376c42SPoonam Aggrwal - While developing some new feature of u-boot, for example USB driver or 2656376c42SPoonam Aggrwal SPI driver. 2756376c42SPoonam Aggrwal Suppose the board already has a working bootloader on it. And you would 2856376c42SPoonam Aggrwal prefer to keep it intact, at the same time want to test your bootloader. 2956376c42SPoonam Aggrwal In this case you can get your test bootloader binary into DDR via tftp 3056376c42SPoonam Aggrwal for example. Then execute the test bootloader. 3156376c42SPoonam Aggrwal - Suppose a platform already has a propreitery bootloader which does not 3256376c42SPoonam Aggrwal support for example AMP boot. In this case also RAM boot loader can be 3356376c42SPoonam Aggrwal utilized. 3456376c42SPoonam Aggrwal 3556376c42SPoonam Aggrwal So basically when the original bootloader is required to be kept intact 3656376c42SPoonam Aggrwal RAM based bootloader can offer an updated bootloader on the system. 3756376c42SPoonam Aggrwal 3856376c42SPoonam AggrwalBoth the above Bootloaders are slight variants of SDcard or SPI Flash 3956376c42SPoonam Aggrwalbootloader or for that matter even NAND bootloader. 4056376c42SPoonam AggrwalAll of them define CONFIG_SYS_RAMBOOT. 4156376c42SPoonam AggrwalThe main difference among all of them is the way the pre-environment is getting 4256376c42SPoonam Aggrwalconfigured and who is doing that. 4356376c42SPoonam Aggrwal- In case of SD card and SPI flash bootloader this is done by On Chip BootROM inside the Si itself. 4456376c42SPoonam Aggrwal- In case of NAND boot SPL/TPL code does it with some support from Si itself. 4556376c42SPoonam Aggrwal- In case of the pure RAM based bootloaders we have to do it by JTAG manually or already existing bootloader. 4656376c42SPoonam Aggrwal 4756376c42SPoonam AggrwalHow to use them: 4856376c42SPoonam Aggrwal1. Using JTAG 4956376c42SPoonam Aggrwal Boot up in core hold off mode or stop the core after reset using JTAG 5056376c42SPoonam Aggrwal interface. 5156376c42SPoonam Aggrwal Preconfigure DDR/L2SRAM through JTAG interface. 5256376c42SPoonam Aggrwal - setup DDR controller registers. 5356376c42SPoonam Aggrwal - setup DDR LAWs 5456376c42SPoonam Aggrwal - setup DDR TLB 5556376c42SPoonam Aggrwal Load the RAM based boot loader to the proper location in DDR/L2SRAM. 5656376c42SPoonam Aggrwal set up IAR (Instruction counter properly) 5756376c42SPoonam Aggrwal Enable the core to execute. 5856376c42SPoonam Aggrwal 5956376c42SPoonam Aggrwal2. Using already existing bootloader. 6056376c42SPoonam Aggrwal get the rambased boot loader binary into DDR/L2SRAM via tftp. 6156376c42SPoonam Aggrwal execute the RAM based bootloader. 6256376c42SPoonam Aggrwal => tftp 11000000 u-boot-ram.bin 6356376c42SPoonam Aggrwal => go 1107f000 6456376c42SPoonam Aggrwal 6556376c42SPoonam AggrwalPlease note that L2SRAM can also be used instead of DDR if the SOC has 6656376c42SPoonam Aggrwalsufficient size of L2SRAM. 6756376c42SPoonam Aggrwal 6856376c42SPoonam AggrwalNecessary Code changes Required: 6956376c42SPoonam Aggrwal===================================== 7056376c42SPoonam AggrwalPlease note that below mentioned changes are for 85xx platforms. 7156376c42SPoonam AggrwalThey have been tested on P1020/P2020/P1010 RDB. 7256376c42SPoonam Aggrwal 7356376c42SPoonam AggrwalThe main difference between the above two methods from technical perspective is 7456376c42SPoonam Aggrwalthat in 1st case SOC is just out of reset so it is in default configuration. 7556376c42SPoonam Aggrwal(CCSRBAR is at 0xff700000). 7656376c42SPoonam AggrwalIn the 2nd case bootloader has already re-located CCSRBAR to 0xffe00000 7756376c42SPoonam Aggrwal 7856376c42SPoonam Aggrwal1. File name-> boards.cfg 7956376c42SPoonam Aggrwal There can be added specific Make options for RAMBoot. We can keep different 8056376c42SPoonam Aggrwal options for the two cases mentioned above. 8156376c42SPoonam Aggrwal for example 8256376c42SPoonam Aggrwal P1020RDB_JTAG_RAMBOOT and P1020RDB_GO_RAMBOOT. 8356376c42SPoonam Aggrwal 8456376c42SPoonam Aggrwal2. platform config file 8556376c42SPoonam Aggrwal for example include/configs/P1_P2_RDB.h 8656376c42SPoonam Aggrwal 8756376c42SPoonam Aggrwal #ifdef CONFIG_RAMBOOT 8856376c42SPoonam Aggrwal #define CONFIG_SDCARD 8956376c42SPoonam Aggrwal #endif 9056376c42SPoonam Aggrwal 9156376c42SPoonam Aggrwal This will finally use the CONFIG_SYS_RAMBOOT. 9256376c42SPoonam Aggrwal 93*830fc1bfSYork Sun3. Change CONFIG_SYS_CCSRBAR_DEFAULT in menuconfig accordingly. 94*830fc1bfSYork Sun In the section of the particular SOC, for example P1020, pseudo code 9556376c42SPoonam Aggrwal 9656376c42SPoonam Aggrwal #if defined(CONFIG_GO) 9756376c42SPoonam Aggrwal #define CONFIG_SYS_CCSRBAR_DEFAULT 0xffe00000 9856376c42SPoonam Aggrwal #else 9956376c42SPoonam Aggrwal #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 10056376c42SPoonam Aggrwal #endif 10156376c42SPoonam Aggrwal 10256376c42SPoonam AggrwalFor JTAG RAMBOOT this is not required because CCSRBAR is at ff700000. 103