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/openbmc/linux/drivers/iommu/
H A Dmsm_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
13 #include <linux/io-pgtable.h>
18 #include <linux/iommu.h>
25 #include "msm_iommu_hw-8xxx.h"
54 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
58 ret = clk_enable(iommu->pclk); in __enable_clocks()
62 if (iommu->clk) { in __enable_clocks()
63 ret = clk_enable(iommu->clk); in __enable_clocks()
65 clk_disable(iommu->pclk); in __enable_clocks()
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H A Dipmmu-vmsa.c1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
29 #include <asm/dma-iommu.h>
32 #define arm_iommu_attach_device(...) -ENODEV
37 #define IPMMU_CTX_INVALID -1
58 struct iommu_device iommu; member
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H A Domap-iommu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * omap iommu: main structures
5 * Copyright (C) 2008-2009 Nokia Corporation
14 #include <linux/iommu.h>
29 * struct omap_iommu_device - omap iommu device data
30 * @pgtable: page table used by an omap iommu attached to a domain
31 * @iommu_dev: pointer to store an omap iommu instance attached to a domain
39 * struct omap_iommu_domain - omap iommu domain
41 * @iommus: omap iommu device data for all iommus in this domain
44 * @domain: generic domain handle used by iommu core code
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H A Domap-iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap iommu: tlb and pagetable primitives
5 * Copyright (C) 2008-2010 Nokia Corporation
6 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
12 #include <linux/dma-mapping.h>
18 #include <linux/iommu.h>
19 #include <linux/omap-iommu.h>
30 #include <linux/platform_data/iommu-omap.h>
32 #include "omap-iopgtable.h"
33 #include "omap-iommu.h"
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/openbmc/linux/arch/sparc/kernel/
H A Diommu.c1 // SPDX-License-Identifier: GPL-2.0
2 /* iommu.c: Generic sparc64 IOMMU support.
13 #include <linux/dma-map-ops.h>
15 #include <linux/iommu-helper.h>
17 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
28 #define STC_CTXMATCH_ADDR(STC, CTX) \ argument
29 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
31 (*((STC)->strbuf_flushflag) = 0UL)
33 (*((STC)->strbuf_flushflag) != 0UL)
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H A Dpci_schizo.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <asm/iommu.h>
46 /* IOMMU control register. */
53 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
54 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
55 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
56 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
57 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
58 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
59 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
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H A Dpci_psycho.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <asm/iommu.h>
61 /* Helper function of IOMMU error checking, which checks out
62 * the state of the streaming buffers. The IOMMU lock is
90 * interrogate the IOMMU state to see if it is the cause.
99 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
100 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
101 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
102 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
103 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
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/openbmc/linux/drivers/iommu/arm/arm-smmu/
H A Dqcom_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
13 #include <linux/dma-mapping.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
33 #include "arm-smmu.h"
47 /* IOMMU core code handle */
48 struct iommu_device iommu; member
62 u8 asid; /* asid and ctx bank # are 1:1 */
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/openbmc/linux/drivers/gpu/host1x/
H A Dcontext.c1 // SPDX-License-Identifier: GPL-2.0-only
23 struct host1x_memory_context_list *cdl = &host1x->context_list; in host1x_memory_context_list_init()
24 struct device_node *node = host1x->dev->of_node; in host1x_memory_context_list_init()
25 struct host1x_memory_context *ctx; in host1x_memory_context_list_init() local
29 cdl->devs = NULL; in host1x_memory_context_list_init()
30 cdl->len = 0; in host1x_memory_context_list_init()
31 mutex_init(&cdl->lock); in host1x_memory_context_list_init()
33 err = of_property_count_u32_elems(node, "iommu-map"); in host1x_memory_context_list_init()
37 cdl->len = err / 4; in host1x_memory_context_list_init()
38 cdl->devs = kcalloc(cdl->len, sizeof(*cdl->devs), GFP_KERNEL); in host1x_memory_context_list_init()
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/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Dqcom,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies legacy IOMMU implementations
10 - Konrad Dybcio <konrad.dybcio@linaro.org>
13 Qualcomm "B" family devices which are not compatible with arm-smmu have
14 a similar looking IOMMU, but without access to the global register space
16 to non-secure vs secure interrupt line.
21 - items:
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/openbmc/qemu/hw/riscv/
H A Driscv-iommu.c2 * QEMU emulation of an RISC-V IOMMU
4 * Copyright (C) 2021-2023, Rivos Inc.
23 #include "hw/qdev-properties.h"
30 #include "riscv-iommu.h"
31 #include "riscv-iommu-bits.h"
48 RISCVIOMMUState *iommu; /* Managing IOMMU device state */ member
50 bool notifier; /* IOMMU unmap notifier enabled */
60 uint64_t satp; /* S-Stage address translation and protection */
61 uint64_t gatp; /* G-Stage address translation and protection */
62 uint64_t msi_addr_mask; /* MSI filtering - address mask */
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/openbmc/linux/drivers/dma/idxd/
H A Dcdev.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/io-64-nonatomic-lo-hi.h>
13 #include <linux/iommu.h>
56 static void idxd_xa_pasid_remove(struct idxd_user_context *ctx);
67 struct idxd_user_context *ctx = dev_to_uctx(dev); in cr_faults_show() local
69 return sysfs_emit(buf, "%llu\n", ctx->counters[COUNTER_FAULTS]); in cr_faults_show()
76 struct idxd_user_context *ctx = dev_to_uctx(dev); in cr_fault_failures_show() local
78 return sysfs_emit(buf, "%llu\n", ctx->counters[COUNTER_FAULT_FAILS]); in cr_fault_failures_show()
84 struct idxd_user_context *ctx = dev_to_uctx(dev); in pid_show() local
86 return sysfs_emit(buf, "%u\n", ctx->pid); in pid_show()
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/openbmc/linux/drivers/gpu/drm/msm/
H A Dmsm_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
8 #include <linux/dma-mapping.h>
9 #include <linux/fault-inject.h>
37 * - 1.0.0 - initial interface
38 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
39 * - 1.2.0 - adds explicit fence support for submit ioctl
40 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
43 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
45 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
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/openbmc/linux/drivers/media/platform/rockchip/rga/
H A Drga-buf.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Jacob Chen <jacob-chen@iotwrt.com>
9 #include <media/v4l2-device.h>
10 #include <media/v4l2-ioctl.h>
11 #include <media/v4l2-mem2mem.h>
12 #include <media/videobuf2-dma-sg.h>
13 #include <media/videobuf2-v4l2.h>
15 #include "rga-hw.h"
23 struct rga_ctx *ctx = vb2_get_drv_priv(vq); in rga_queue_setup() local
24 struct rga_frame *f = rga_get_frame(ctx, vq->type); in rga_queue_setup()
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/openbmc/linux/drivers/accel/ivpu/
H A Divpu_gem.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2023 Intel Corporation
6 #include <linux/dma-buf.h>
31 /* Pages are managed by the underlying dma-buf */ in prime_alloc_pages_locked()
37 /* Pages are managed by the underlying dma-buf */ in prime_free_pages_locked()
45 sgt = dma_buf_map_attachment_unlocked(bo->base.import_attach, DMA_BIDIRECTIONAL); in prime_map_pages_locked()
51 bo->sgt = sgt; in prime_map_pages_locked()
57 dma_buf_unmap_attachment_unlocked(bo->base.import_attach, bo->sgt, DMA_BIDIRECTIONAL); in prime_unmap_pages_locked()
58 bo->sgt = NULL; in prime_unmap_pages_locked()
72 int npages = bo->base.size >> PAGE_SHIFT; in shmem_alloc_pages_locked()
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/openbmc/linux/drivers/gpu/drm/exynos/
H A Dexynos7_drm_decon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #include "regs-decon7.h"
62 {.compatible = "samsung,exynos7-decon"},
86 struct decon_context *ctx = crtc->ctx; in decon_wait_for_vblank() local
88 if (ctx->suspended) in decon_wait_for_vblank()
91 atomic_set(&ctx->wait_vsync_event, 1); in decon_wait_for_vblank()
97 if (!wait_event_timeout(ctx->wait_vsync_queue, in decon_wait_for_vblank()
98 !atomic_read(&ctx->wait_vsync_event), in decon_wait_for_vblank()
100 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); in decon_wait_for_vblank()
105 struct decon_context *ctx = crtc->ctx; in decon_clear_channels() local
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H A Dexynos5433_drm_decon.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "regs-decon5433.h"
96 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, in decon_set_bits() argument
99 val = (val & mask) | (readl(ctx->addr + reg) & ~mask); in decon_set_bits()
100 writel(val, ctx->addr + reg); in decon_set_bits()
105 struct decon_context *ctx = crtc->ctx; in decon_enable_vblank() local
109 if (crtc->i80_mode) in decon_enable_vblank()
114 writel(val, ctx->addr + DECON_VIDINTCON0); in decon_enable_vblank()
116 enable_irq(ctx->irq); in decon_enable_vblank()
117 if (!(ctx->out_type & I80_HW_TRG)) in decon_enable_vblank()
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/openbmc/qemu/include/sysemu/
H A Ddma.h14 #include "exec/address-spaces.h"
24 * When an IOMMU is present, bus addresses become distinct from
27 * or less have to treat these as 64-bit always to cover all (or at
115 * IOMMU fault).
138 * IOMMU fault). Called within RCU critical section.
159 * IOMMU fault).
180 * IOMMU fault).
197 * Use only for reads OR writes - not for read-modify-write operations.
293 BlockAIOCB *dma_blk_io(AioContext *ctx,
313 * power of 2 size less or equal than @end - @start + 1, aligned with @start,
/openbmc/linux/drivers/crypto/caam/
H A Dcaamalg_qi2.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * Copyright 2015-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2018 NXP
12 #include <soc/fsl/dpaa2-io.h>
13 #include <soc/fsl/dpaa2-fd.h>
30 * dpaa2_caam_priv - driver private data
43 * @domain: IOMMU domain
71 * dpaa2_caam_priv_per_cpu - per CPU private data
76 * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr
98 * aead_edesc - s/w-extended aead descriptor
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/thermal/thermal.h>
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H A Dmsm8939.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8939.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
13 #include <dt-bindings/thermal/thermal.h>
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H A Dmsm8953.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
4 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/soc/qcom,apr.h>
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-bindings/sound/qcom,q6asm.h>
12 #include <dt-bindings/thermal/thermal.h>
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/openbmc/qemu/hw/i386/
H A Dacpi-build.c3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
26 #include "acpi-build.h"
27 #include "acpi-common.h"
29 #include "qemu/error-report.h"
35 #include "hw/acpi/acpi-defs.h"
39 #include "hw/acpi/bios-linker-loader.h"
51 #include "hw/mem/memory-device.h"
55 #include "hw/hyperv/vmbus-bridge.h"
63 #include "hw/pci-host/i440fx.h"
64 #include "hw/pci-host/q35.h"
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/openbmc/linux/drivers/vhost/
H A Dvdpa.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2020 Intel Corporation.
20 #include <linux/iommu.h>
76 return as->id; in iotlb_to_asid()
81 struct hlist_head *head = &v->as[asid % VHOST_VDPA_IOTLB_BUCKETS]; in asid_to_as()
85 if (as->id == asid) in asid_to_as()
98 return &as->iotlb; in asid_to_iotlb()
103 struct hlist_head *head = &v->as[asid % VHOST_VDPA_IOTLB_BUCKETS]; in vhost_vdpa_alloc_as()
109 if (asid >= v->vdpa->nas) in vhost_vdpa_alloc_as()
116 vhost_iotlb_init(&as->iotlb, 0, 0); in vhost_vdpa_alloc_as()
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/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dsnoc.c1 // SPDX-License-Identifier: ISC
17 #include <linux/iommu.h>
46 "vdd-0.8-cx-mx",
47 "vdd-1.8-xo",
48 "vdd-1.3-rfa",
49 "vdd-3.3-ch0",
50 "vdd-3.3-ch1",
136 /* CE0: host->target HTC control streams */
145 /* CE1: target->host HTT + HTC control */
154 /* CE2: target->host WMI */
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