2  * RISC-V IOMMU - Hardware Performance Monitor (HPM) helpers
4  * Copyright (C) 2022-2023 Rivos Inc.
22 #include "riscv-iommu-hpm.h"
23 #include "riscv-iommu.h"
24 #include "riscv-iommu-bits.h"
27 /* For now we assume IOMMU HPM frequency to be 1GHz so 1-cycle is of 1-ns. */
39     const uint64_t ctr_prev = s->hpmcycle_prev;  in riscv_iommu_hpmcycle_read()
40     const uint64_t ctr_val = s->hpmcycle_val;  in riscv_iommu_hpmcycle_read()
54     return (ctr_val + get_cycles() - ctr_prev) |  in riscv_iommu_hpmcycle_read()
63     cntr_val = ldq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off]);  in hpm_incr_ctr()
64     stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off], cntr_val + 1);  in hpm_incr_ctr()
87 void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,  in riscv_iommu_hpm_incr_ctr()  argument
99     if (!(s->cap & RISCV_IOMMU_CAP_HPM)) {  in riscv_iommu_hpm_incr_ctr()
103     value = g_hash_table_lookup(s->hpm_event_ctr_map,  in riscv_iommu_hpm_incr_ctr()
109     for (ctrs = GPOINTER_TO_UINT(value); ctrs != 0; ctrs &= ctrs - 1) {  in riscv_iommu_hpm_incr_ctr()
128             did_gscid = get_field(ctx->gatp, RISCV_IOMMU_DC_IOHGATP_GSCID);  in riscv_iommu_hpm_incr_ctr()
129             pid_pscid = get_field(ctx->ta, RISCV_IOMMU_DC_TA_PSCID);  in riscv_iommu_hpm_incr_ctr()
131             did_gscid = ctx->devid;  in riscv_iommu_hpm_incr_ctr()
132             pid_pscid = ctx->process_id;  in riscv_iommu_hpm_incr_ctr()
141              * IOMMU Specification, Chapter 5.23. Performance-monitoring  in riscv_iommu_hpm_incr_ctr()
144             if (ctx->process_id &&  in riscv_iommu_hpm_incr_ctr()
186     if (s->irq_overflow_left > 0) {  in riscv_iommu_hpm_timer_cb()
188             qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->irq_overflow_left;  in riscv_iommu_hpm_timer_cb()
189         timer_mod_anticipate_ns(s->hpm_timer, irq_trigger_at);  in riscv_iommu_hpm_timer_cb()
190         s->irq_overflow_left = 0;  in riscv_iommu_hpm_timer_cb()
222      * has 63-bit precision and INT64_MAX is the maximum it can store.  in hpm_setup_timer()
225         overflow_ns = INT64_MAX - value + 1;  in hpm_setup_timer()
233         s->irq_overflow_left = overflow_at - INT64_MAX;  in hpm_setup_timer()
237     timer_mod_anticipate_ns(s->hpm_timer, overflow_at);  in hpm_setup_timer()
259         s->hpmcycle_prev = get_cycles();  in riscv_iommu_process_iocntinh_cy()
260         hpm_setup_timer(s, s->hpmcycle_val);  in riscv_iommu_process_iocntinh_cy()
267         s->hpmcycle_val = s->hpmcycle_val + (get_cycles() - s->hpmcycle_prev);  in riscv_iommu_process_iocntinh_cy()
268         timer_del(s->hpm_timer);  in riscv_iommu_process_iocntinh_cy()
288     s->hpmcycle_val = val & ~RISCV_IOMMU_IOHPMCYCLES_OVF;  in riscv_iommu_process_hpmcycle_write()
289     s->hpmcycle_prev = get_cycles();  in riscv_iommu_process_hpmcycle_write()
290     hpm_setup_timer(s, s->hpmcycle_val);  in riscv_iommu_process_hpmcycle_write()
325         data = g_hash_table_find(s->hpm_event_ctr_map, hpm_event_equal, pair);  in update_event_map()
329             g_hash_table_replace(s->hpm_event_ctr_map,  in update_event_map()
333             g_hash_table_remove(s->hpm_event_ctr_map,  in update_event_map()
341     if (g_hash_table_lookup_extended(s->hpm_event_ctr_map,  in update_event_map()
348     g_hash_table_insert(s->hpm_event_ctr_map,  in update_event_map()
355     const uint32_t ctr_idx = (evt_reg - RISCV_IOMMU_REG_IOHPMEVT_BASE) >> 3;  in riscv_iommu_process_hpmevt_write()
359     if (ctr_idx >= s->hpm_cntrs) {  in riscv_iommu_process_hpmevt_write()