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/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dxilinx,can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
31 clock-names:
34 power-domains:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Daltr,tse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Chevallier <maxime.chevallier@bootlin.com>
15 - const: altr,tse-1.0
16 - const: ALTR,tse-1.0
18 - const: altr,tse-msgdma-1.0
23 interrupt-names:
25 - const: rx_irq
26 - const: tx_irq
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H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
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H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
33 adi,fifo-depth-bits:
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/openbmc/u-boot/doc/device-tree-bindings/net/
H A Daltera_tse.txt1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
6 - reg: Address and length of the register set for the device. It contains
7 the information of registers in the same order as described by reg-names
8 - reg-names: Should contain the reg names
16 - interrupts: Should contain the TSE interrupts and it's mode.
17 - interrupt-names: Should contain the interrupt names
20 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
21 - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
[all …]
H A Dti,dp83867.txt1 * Texas Instruments - dp83867 Giga bit ethernet phy
4 - reg - The ID number for the phy, usually a small integer
5 - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
7 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
9 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
11 - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
13 - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
15 - ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h
23 ethernet-phy@0 {
25 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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/openbmc/linux/drivers/staging/axis-fifo/
H A Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
[all …]
H A Daxis-fifo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
12 /* ----------------------------
14 * ----------------------------
37 /* ----------------------------
39 * ----------------------------
47 /* ----------------------------
49 * ----------------------------
68 /* ----------------------------
70 * ----------------------------
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/openbmc/linux/sound/soc/meson/
H A Daxg-fifo.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
15 #include <sound/soc-dai.h>
17 #include "axg-fifo.h"
21 * capture frontend DAI. The logic behind this two types of fifo is very
49 struct snd_soc_pcm_runtime *rtd = ss->private_data; in axg_fifo_dai()
65 return dai->dev; in axg_fifo_dev()
68 static void __dma_enable(struct axg_fifo *fifo, bool enable) in __dma_enable() argument
70 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN, in __dma_enable()
77 struct axg_fifo *fifo = axg_fifo_data(ss); in axg_fifo_pcm_trigger() local
83 __dma_enable(fifo, true); in axg_fifo_pcm_trigger()
[all …]
H A Daxg-frddr.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
17 #include <sound/soc-dai.h>
19 #include "axg-fifo.h"
38 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); in g12a_frddr_dai_prepare() local
41 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
55 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); in axg_frddr_dai_hw_params() local
56 unsigned int period, depth, val; in axg_frddr_dai_hw_params() local
60 /* Trim the FIFO depth if the period is small to improve latency */ in axg_frddr_dai_hw_params()
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dcdns,qspi-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
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H A Dspi-sifive.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: spi-controller.yaml#
20 - enum:
21 - sifive,fu540-c000-spi
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Damlogic,axg-fifo.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/amlogic,axg-fifo.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic AXG Audio FIFO controllers
10 - Jerome Brunet <jbrunet@baylibre.com>
15 - enum:
16 - amlogic,axg-toddr
17 - amlogic,axg-frddr
18 - items:
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/openbmc/linux/include/linux/soc/qcom/
H A Dgeni-se.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
15 * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO
56 * struct geni_se - GENI Serial Engine
258 * For QUP HW Version >= 3.10 Tx fifo depth support is increased
269 * For QUP HW Version >= 3.10 Rx fifo depth support is increased
309 * geni_se_read_proto() - Read the protocol configured for a serial engine
318 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); in geni_se_read_proto()
324 * geni_se_setup_m_cmd() - Setup the primary sequencer
337 writel(m_cmd, se->base + SE_GENI_M_CMD0); in geni_se_setup_m_cmd()
[all …]
/openbmc/linux/Documentation/networking/device_drivers/can/freescale/
H A Dflexcan.rst1 .. SPDX-License-Identifier: GPL-2.0+
7 Authors: Marc Kleine-Budde <mkl@pengutronix.de>,
15 - FIFO
16 - mailbox
20 configured for RX-FIFO mode.
22 The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames,
23 while the mailbox mode uses a software FIFO with a depth of up to 62
30 With the "rx-rtr" private flag the ability to receive RTR frames can
34 "rx-rtr" on
40 more performant "RX mailbox" mode and will use "RX FIFO" mode
[all …]
/openbmc/qemu/hw/audio/
H A Dpl041.c5 * Written by Mathieu Sonet - www.elasticsheep.com
15 * - Supports only a playback on one channel (Versatile/Vexpress)
16 * - Supports only one TX FIFO in compact-mode or non-compact mode.
17 * - Supports playback of 12, 16, 18 and 20 bits samples.
18 * - Record is not supported.
19 * - The PL041 is hardwired to a LM4549 codec.
25 #include "hw/qdev-properties.h"
61 /* This FIFO only stores 20-bit samples on 32-bit words.
89 uint32_t fifo_depth; /* FIFO depth in non-compact mode */
125 /* Add the fifo depth information */ in pl041_compute_periphid3()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dcdns,i2c-r1p10.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - cdns,i2c-r1p10 # cadence i2c controller version 1.0
19 - cdns,i2c-r1p14 # cadence i2c controller version 1.4
33 clock-frequency:
39 clock-name:
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/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-sm1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-sm1-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
16 tdmif_a: audio-controller-0 {
17 compatible = "amlogic,axg-tdm-iface";
18 #sound-dai-cells = <0>;
19 sound-name-prefix = "TDM_A";
[all …]
H A Dmeson-g12.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-g12a-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
14 tdmif_a: audio-controller-0 {
15 compatible = "amlogic,axg-tdm-iface";
16 #sound-dai-cells = <0>;
17 sound-name-prefix = "TDM_A";
[all …]
/openbmc/u-boot/drivers/i2c/
H A Dxilinx_xiic.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Based on Linux 4.14.y i2c-xiic.c
8 * Copyright (c) 2002-2007 Xilinx Inc.
9 * Copyright (c) 2009-2010 Intel Corporation
36 #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
37 #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
39 #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
44 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
55 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
56 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
[all …]
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/openbmc/qemu/include/hw/char/
H A Dpl011.h19 #include "chardev/char-fe.h"
28 /* Depth of UART FIFO in bytes, when FIFO mode is enabled (else depth == 1) */
/openbmc/linux/drivers/spi/
H A Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
24 #define CDNS_SPI_NAME "cdns-spi"
37 #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
62 * SPI Configuration Register - Baud rate and target select
81 #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
83 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
101 * struct cdns_spi - This definition defines spi driver instance
113 * @tx_fifo_depth: Depth of the TX FIFO
[all …]

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