| /openbmc/openbmc/poky/meta/conf/machine/include/microblaze/ |
| H A D | arch-microblaze.inc | 7 # 64-bit
8 TUNEVALID[64-bit] = "64-bit MicroBlaze"
9 TUNECONFLICTS[64-bit] = "v8.00 v8.10 v8.20 v8.30 v8.40 v8.50 v9.0 v9.1 v9.2 v9.3 v9.4 v9.5 v9.6 v10…
10 MACHINEOVERRIDES =. "${@bb.utils.contains("TUNE_FEATURES", "64-bit", "microblaze64:", "", d)}"
18 TUNE_CCARGS .= "${@bb.utils.contains("TUNE_FEATURES", "bigendian", " -mbig-endian", " -mlittle-endi…
21 TUNEVALID[barrel-shift] = "Enable Hardware Barrel Shifter"
22 TUNEVALID[pattern-compare] = "Enable Pattern Compare Instructions"
23 TUNEVALID[reorder] = "Enable Reorder Instructions"
27 TUNEVALID[frequency-optimized] = "Enabling tuning for frequency optimized core (AREA_OPTIMIZED_2)"
28 TUNECONFLICTS[frequency-optimized] = "v8.00 v8.10 v8.20 v8.30 v8.40 v8.50 v9.0 v9.1 v9.2 v9.3 v9.4 …
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| /openbmc/linux/arch/arm64/boot/dts/intel/ |
| H A D | keembay-soc.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
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| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
100 * @shift: shift to the divider bit field
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
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| /openbmc/linux/include/linux/ |
| H A D | clocksource.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
35 * struct clocksource - hardware abstraction for a free running counter
36 * Provides mostly state-free accessors to the underlying hardware.
43 * @shift: Cycle to nanosecond divisor (power of two)
48 * @archdata: Optional arch-specific data
57 * 1-99: Unfit for real use
59 * 100-199: Base level usability.
61 * 200-299: Good.
63 * 300-399: Desired.
65 * 400-499: Perfect
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | apll.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped APLL with usually two selectable input clocks
13 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
18 - #clock-cells : from common clock binding; shall be set to 0.
19 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
20 - reg : address and length of the register set for controlling the APLL.
22 "control" - contains the control register offset
23 "idlest" - contains the idlest register offset
24 "autoidle" - contains the autoidle register offset (OMAP2 only)
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| /openbmc/linux/drivers/pwm/ |
| H A D | pwm-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
64 return __raw_readl(p->base + offset); in brcmstb_pwm_readl()
66 return readl_relaxed(p->base + offset); in brcmstb_pwm_readl()
73 __raw_writel(value, p->base + offset); in brcmstb_pwm_writel()
75 writel_relaxed(value, p->base + offset); in brcmstb_pwm_writel()
84 * Fv is derived from the variable frequency output. The variable frequency
87 * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
89 * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
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| /openbmc/linux/drivers/net/ethernet/intel/ixgbe/ |
| H A D | ixgbe_ptp.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
16 * clock frequency of the oscillator in combination with the TIMINCA
21 * of only a right shift (division by power of 2). The following math
30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
40 * The calculated value allows us to right shift the SYSTIME register
47 * +--------------+ +--------------+
49 * *--------------+ +--------------+
52 * +--------------+ +--------------+
54 * *--------------+ +--------------+
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| /openbmc/linux/arch/arm64/boot/dts/amazon/ |
| H A D | alpine-v2.dtsi | 4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
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| /openbmc/linux/drivers/clk/bcm/ |
| H A D | clk-iproc-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
27 /* number of VCO frequency bands */
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
102 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
103 vco_out->ndiv_frac = ndiv_frac; in pll_calc_param()
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| H A D | clk-iproc.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
17 #define bit_mask(width) ((1 << (width)) - 1)
62 * auto calculates VCO frequency parameters based on the provided leaf
79 * Parameters for VCO frequency configuration
81 * VCO frequency =
82 * ((ndiv_int + ndiv_frac / 2^20) * (ref frequency / pdiv)
93 unsigned int shift; member
140 * To enable SW control of the PLL
144 unsigned int shift; member
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| /openbmc/linux/drivers/clk/sunxi-ng/ |
| H A D | ccu_mux.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
24 if (!((common->features & CCU_FEATURE_FIXED_PREDIV) || in ccu_mux_get_prediv()
25 (common->features & CCU_FEATURE_VARIABLE_PREDIV) || in ccu_mux_get_prediv()
26 (common->features & CCU_FEATURE_ALL_PREDIV))) in ccu_mux_get_prediv()
29 if (common->features & CCU_FEATURE_ALL_PREDIV) in ccu_mux_get_prediv()
30 return common->prediv; in ccu_mux_get_prediv()
32 reg = readl(common->base + common->reg); in ccu_mux_get_prediv()
34 parent_index = reg >> cm->shift; in ccu_mux_get_prediv()
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| /openbmc/linux/include/uapi/linux/ |
| H A D | timex.h | 28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
62 * syscall interface - used (mainly by NTP daemon)
68 __kernel_long_t freq; /* frequency offset (scaled ppm) */
74 __kernel_long_t tolerance;/* clock frequency tolerance (ppm)
80 __kernel_long_t ppsfreq;/* pps frequency (scaled ppm) (ro) */
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| /openbmc/linux/arch/arm64/boot/dts/realtek/ |
| H A D | rtd16xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
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| /openbmc/linux/Documentation/devicetree/bindings/regulator/ |
| H A D | maxim,max8973.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: regulator.yaml#
18 - maxim,max8973
19 - maxim,max77621
21 junction-warn-millicelsius:
30 maxim,dvs-gpio:
35 maxim,dvs-default-state:
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| /openbmc/u-boot/doc/device-tree-bindings/serial/ |
| H A D | 8250.txt | 4 - compatible : one of:
5 - "ns8250"
6 - "ns16450"
7 - "ns16550a"
8 - "ns16550"
9 - "ns16750"
10 - "ns16850"
11 - For Tegra20, must contain "nvidia,tegra20-uart"
12 - For other Tegra, must contain '"nvidia,<chip>-uart",
13 "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
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| /openbmc/linux/drivers/clk/sunxi/ |
| H A D | clk-sunxi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
46 req->rate == 54000000) in sun4i_get_pll1_factors()
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| /openbmc/linux/drivers/clk/actions/ |
| H A D | owl-pll.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 // Author: David Liu <liuwei@actions-semi.com>
11 #include <linux/clk-provider.h>
16 #include "owl-pll.h"
22 mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq); in owl_pll_calculate_mul()
23 if (mul < pll_hw->min_mul) in owl_pll_calculate_mul()
24 mul = pll_hw->min_mul; in owl_pll_calculate_mul()
25 else if (mul > pll_hw->max_mul) in owl_pll_calculate_mul()
26 mul = pll_hw->max_mul; in owl_pll_calculate_mul()
36 for (clkt = table; clkt->rate; clkt++) in _get_table_rate()
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| /openbmc/linux/drivers/net/ethernet/mellanox/mlx4/ |
| H A D | en_clock.c | 14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
39 /* mlx4_en_read_clock - read raw cycle counter (to be used by time counter)
45 struct mlx4_dev *dev = mdev->dev; in mlx4_en_read_clock()
47 return mlx4_read_clock(dev) & tc->mask; in mlx4_en_read_clock()
55 lo = (u64)be16_to_cpu(ts_cqe->timestamp_lo); in mlx4_en_get_cqe_ts()
56 hi = ((u64)be32_to_cpu(ts_cqe->timestamp_hi) + !lo) << 16; in mlx4_en_get_cqe_ts()
67 seq = read_seqbegin(&mdev->clock_lock); in mlx4_en_get_hwtstamp()
68 nsec = timecounter_cyc2time(&mdev->clock, timestamp); in mlx4_en_get_hwtstamp()
69 } while (read_seqretry(&mdev->clock_lock, seq)); in mlx4_en_get_hwtstamp()
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| /openbmc/qemu/hw/audio/ |
| H A D | fmopl.h | 10 /* ---------- OPL one of slot ---------- */
14 uint8_t KSR; /* key scale rate :(shift down bit) */
19 uint8_t ksl; /* keyscale level :(shift down bits) */
22 uint32_t Cnt; /* frequency count : */
23 uint32_t Incr; /* frequency step : */
40 /* ---------- OPL one of channel ---------- */
44 uint8_t FB; /* feed back :(shift down bit) */
60 double freqbase; /* frequency base */
68 uint8_t st[2]; /* timer enable */
77 uint32_t FN_TABLE[1024]; /* fnumber -> increment counter */
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| /openbmc/linux/arch/arm/boot/dts/broadcom/ |
| H A D | bcm23550.dtsi | 34 #include <dt-bindings/clock/bcm21664.h>
35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/interrupt-controller/irq.h>
39 #address-cells = <1>;
40 #size-cells = <1>;
43 interrupt-parent = <&gic>;
46 #address-cells = <1>;
47 #size-cells = <0>;
51 compatible = "arm,cortex-a7";
53 clock-frequency = <1000000000>;
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | clock.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
29 * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
43 /* return the current oscillator clock frequency */
46 /* return the clk_m frequency */
65 * Set PLL output frequency
71 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
77 * Read low-level parameters of a PLL.
86 * @returns 0 if ok, -1 on error (invalid clock id)
92 * Enable a clock
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| /openbmc/linux/arch/microblaze/kernel/ |
| H A D | timer.c | 2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012-2013 Xilinx, Inc.
4 * Copyright (C) 2007-2009 PetaLogix
88 * !ENALL - don't enable 'em all in xilinx_timer0_start_periodic()
89 * !PWMA - disable pwm in xilinx_timer0_start_periodic()
90 * TINT - clear interrupt status in xilinx_timer0_start_periodic()
91 * ENT- enable timer itself in xilinx_timer0_start_periodic()
92 * ENIT - enable interrupt in xilinx_timer0_start_periodic()
93 * !LOAD - clear the bit to let go in xilinx_timer0_start_periodic()
94 * ARHT - auto reload in xilinx_timer0_start_periodic()
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | time.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Converted for 64-bit by Mike Corrigan (mikejc@us.ibm.com)
11 * to make clock more stable (2.4.0-test5). The only thing
20 * - improve precision and reproducibility of timebase frequency
22 * - for astronomical applications: add a new function to get
26 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
50 #include <linux/posix-timers.h>
179 deltascaled = nowscaled - acct->startspurr; in vtime_delta_scaled()
180 acct->startspurr = nowscaled; in vtime_delta_scaled()
181 utime = acct->utime - acct->utime_sspurr; in vtime_delta_scaled()
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| /openbmc/linux/Documentation/devicetree/bindings/serial/ |
| H A D | 8250.yaml | 3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
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| /openbmc/linux/arch/arm/boot/dts/rockchip/ |
| H A D | rv1126.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
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