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/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dst,st-mipid02.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
15 active at a time. Active port input stream will be de-serialized
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
30 vdd-supply:
33 vddio-supply:
36 stby-gpios:
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H A Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
24 - ti,sn65dsi84
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/openbmc/u-boot/arch/arm/dts/
H A Darmada-8040-db.dts4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
47 #include "armada-8040.dtsi"
51 compatible = "marvell,armada8040-db", "marvell,armada8040",
52 "marvell,armada-ap806-quad", "marvell,armada-ap806";
55 stdout-path = "serial0:115200n8";
69 /* Accessible over the mini-USB CON9 connector on the main board */
76 * SDIO [0-10]
80 pin-func = < 1 1 1 1 1 1 1 1 1 1
85 pinctrl-names = "default";
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H A Darmada-xp-mv78230.dtsi6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
62 #address-cells = <1>;
63 #size-cells = <0>;
64 enable-method = "marvell,armada-xp-smp";
68 compatible = "marvell,sheeva-v7";
71 clock-latency = <1000000>;
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H A Darmada-xp-maxbcm.dts4 * Copyright (C) 2013-2014 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
51 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
58 /dts-v1/;
59 #include <dt-bindings/gpio/gpio.h>
60 #include "armada-xp-mv78460.dtsi"
64 …compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370…
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H A Darmada-xp-mv78260.dtsi6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
63 #address-cells = <1>;
64 #size-cells = <0>;
65 enable-method = "marvell,armada-xp-smp";
69 compatible = "marvell,sheeva-v7";
72 clock-latency = <1000000>;
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H A Darmada-xp-gp.dts3 * (DB-MV784MP-GP)
5 * Copyright (C) 2013-2014 Marvell
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
52 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
59 /dts-v1/;
60 #include <dt-bindings/gpio/gpio.h>
61 #include "armada-xp-mv78460.dtsi"
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H A Darmada-xp-mv78460.dtsi6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
64 #address-cells = <1>;
65 #size-cells = <0>;
66 enable-method = "marvell,armada-xp-smp";
70 compatible = "marvell,sheeva-v7";
73 clock-latency = <1000000>;
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H A Darmada-375-db.dts3 * (DB-88F6720)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
49 /dts-v1/;
50 #include <dt-bindings/gpio/gpio.h>
51 #include "armada-375.dtsi"
55 compatible = "marvell,a375-db", "marvell,armada375";
58 stdout-path = "serial0:115200n8";
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H A Darmada-xp-theadorable.dts4 * Copyright (C) 2013-2014 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
51 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
58 /dts-v1/;
59 #include <dt-bindings/gpio/gpio.h>
60 #include "armada-xp-mv78260.dtsi"
64 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
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H A Darmada-385-turris-omnia.dts4 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
41 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
44 /dts-v1/;
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/input/input.h>
48 #include "armada-385.dtsi"
52 compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
55 stdout-path = &uart0;
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/openbmc/linux/drivers/net/dsa/b53/
H A Db53_serdes.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
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/openbmc/linux/include/linux/phy/
H A Dphy-lvds.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_lvds - LVDS configuration set
11 * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential
16 * data lanes, starting from lane 0,
20 * phy to support dual link transmission,
/openbmc/u-boot/board/freescale/t208xqds/
H A DREADME1 The T2080QDS is a high-performance computing evaluation, development and
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
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/openbmc/linux/Documentation/devicetree/bindings/connector/
H A Dusb-connector.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
20 - enum:
21 - usb-a-connector
22 - usb-b-connector
23 - usb-c-connector
25 - items:
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/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dhigh_speed_env_spec-38x.c1 // SPDX-License-Identifier: GPL-2.0
66 case MV_6811: /* A381/A3282: 6811/6821: single/dual cpu */ in hws_serdes_get_max_lane()
85 /* Maximum lane count for A388 (6828) is 6 */ in hws_is_serdes_active()
89 /* 4th Lane (#4 on Device 6810 is not Active */ in hws_is_serdes_active()
91 printf("%s: Error: Lane#4 on Device 6810 is not Active.\n", in hws_is_serdes_active()
97 * 6th Lane (#5) on Device 6810 is Active, even though 6810 in hws_is_serdes_active()
123 * INPUT: serdes_num - Serdes number
124 * serdes_type - Serdes type
/openbmc/linux/drivers/phy/intel/
H A Dphy-intel-lgm-combo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
20 #include <dt-bindings/phy/phy.h>
33 #define CR_ADDR(addr, lane) (((addr) + (lane) * 0x100) << 2) argument
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
114 return regmap_update_bits(cbphy->hsiocfg, REG_CLK_DISABLE(cbphy->bid), in intel_cbphy_iphy_enable()
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/openbmc/linux/drivers/gpu/drm/bridge/
H A Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
35 /* DSI D-PHY Layer Registers */
36 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
43 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
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H A Dtc358762.c1 // SPDX-License-Identifier: GPL-2.0
35 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
36 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
40 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
41 #define DSI_LANEENABLE 0x0210 /* Enables each lane */
66 /* Lane enable PPI and DSI register bits */
84 int ret = ctx->error; in tc358762_clear_error()
86 ctx->error = 0; in tc358762_clear_error()
92 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in tc358762_write()
96 if (ctx->error) in tc358762_write()
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/openbmc/u-boot/board/freescale/t208xrdb/
H A DREADME1 T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
[all …]
/openbmc/linux/drivers/gpu/drm/
H A Ddrm_of.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/media-bus-format.h>
25 * drm_of_crtc_port_mask - find the mask of a registered CRTC by port OF node
39 if (tmp->port == port) in drm_of_crtc_port_mask()
50 * drm_of_find_possible_crtcs - find the possible CRTCs for an encoder port
83 * drm_of_component_match_add - Add a component helper OF node match rule
101 * drm_of_component_probe - Generic probe function for a component based master
121 if (!dev->of_node) in drm_of_component_probe()
122 return -EINVAL; in drm_of_component_probe()
129 port = of_parse_phandle(dev->of_node, "ports", i); in drm_of_component_probe()
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dicl_dsi.c71 drm_err(&dev_priv->drm, "DSI header credits not released\n"); in wait_for_header_credits()
83 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in wait_for_cmds_dispatched_to_panel()
108 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
115 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
116 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
117 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
118 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
121 drm_err(&dev_priv->drm, in wait_for_cmds_dispatched_to_panel()
126 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
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/openbmc/linux/drivers/ufs/host/
H A Dtc-dwc-g210.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
15 #include "ufshcd-dwc.h"
16 #include "ufshci-dwc.h"
17 #include "tc-dwc-g210.h"
20 * tc_dwc_g210_setup_40bit_rmmi() - configure 40-bit RMMI.
23 * Return: 0 on success or non-zero value on failure.
83 * tc_dwc_g210_setup_20bit_rmmi_lane0() - configure 20-bit RMMI Lane 0.
86 * Return: 0 on success or non-zero value on failure.
135 * tc_dwc_g210_setup_20bit_rmmi_lane1() - configure 20-bit RMMI Lane 1.
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/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
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