xref: /openbmc/u-boot/arch/arm/dts/armada-8040-db.dts (revision 9c2369a554437f072733c53ba0f5f5384f35b6d3)
1bf2150b9SStefan Roese/*
2bf2150b9SStefan Roese * Copyright (C) 2016 Marvell Technology Group Ltd.
3bf2150b9SStefan Roese *
4bf2150b9SStefan Roese * This file is dual-licensed: you can use it either under the terms
5bf2150b9SStefan Roese * of the GPLv2 or the X11 license, at your option. Note that this dual
6bf2150b9SStefan Roese * licensing only applies to this file, and not this project as a
7bf2150b9SStefan Roese * whole.
8bf2150b9SStefan Roese *
9bf2150b9SStefan Roese *  a) This library is free software; you can redistribute it and/or
10bf2150b9SStefan Roese *     modify it under the terms of the GNU General Public License as
11bf2150b9SStefan Roese *     published by the Free Software Foundation; either version 2 of the
12bf2150b9SStefan Roese *     License, or (at your option) any later version.
13bf2150b9SStefan Roese *
14bf2150b9SStefan Roese *     This library is distributed in the hope that it will be useful,
15bf2150b9SStefan Roese *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16bf2150b9SStefan Roese *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17bf2150b9SStefan Roese *     GNU General Public License for more details.
18bf2150b9SStefan Roese *
19bf2150b9SStefan Roese * Or, alternatively,
20bf2150b9SStefan Roese *
21bf2150b9SStefan Roese *  b) Permission is hereby granted, free of charge, to any person
22bf2150b9SStefan Roese *     obtaining a copy of this software and associated documentation
23bf2150b9SStefan Roese *     files (the "Software"), to deal in the Software without
24bf2150b9SStefan Roese *     restriction, including without limitation the rights to use,
25bf2150b9SStefan Roese *     copy, modify, merge, publish, distribute, sublicense, and/or
26bf2150b9SStefan Roese *     sell copies of the Software, and to permit persons to whom the
27bf2150b9SStefan Roese *     Software is furnished to do so, subject to the following
28bf2150b9SStefan Roese *     conditions:
29bf2150b9SStefan Roese *
30bf2150b9SStefan Roese *     The above copyright notice and this permission notice shall be
31bf2150b9SStefan Roese *     included in all copies or substantial portions of the Software.
32bf2150b9SStefan Roese *
33bf2150b9SStefan Roese *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34bf2150b9SStefan Roese *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35bf2150b9SStefan Roese *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36bf2150b9SStefan Roese *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37bf2150b9SStefan Roese *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38bf2150b9SStefan Roese *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39bf2150b9SStefan Roese *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40bf2150b9SStefan Roese *     OTHER DEALINGS IN THE SOFTWARE.
41bf2150b9SStefan Roese */
42bf2150b9SStefan Roese
43bf2150b9SStefan Roese/*
44bf2150b9SStefan Roese * Device Tree file for Marvell Armada 8040 Development board platform
45bf2150b9SStefan Roese */
46bf2150b9SStefan Roese
47bf2150b9SStefan Roese#include "armada-8040.dtsi"
48bf2150b9SStefan Roese
49bf2150b9SStefan Roese/ {
50bf2150b9SStefan Roese	model = "Marvell Armada 8040 DB board";
51bf2150b9SStefan Roese	compatible = "marvell,armada8040-db", "marvell,armada8040",
52bf2150b9SStefan Roese		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
53bf2150b9SStefan Roese
54bf2150b9SStefan Roese	chosen {
55bf2150b9SStefan Roese		stdout-path = "serial0:115200n8";
56bf2150b9SStefan Roese	};
57bf2150b9SStefan Roese
58af4c271cSStefan Roese	aliases {
59af4c271cSStefan Roese		i2c0 = &cpm_i2c0;
605b613d38SKonstantin Porotchkin		spi0 = &cps_spi1;
61af4c271cSStefan Roese	};
62af4c271cSStefan Roese
63bf2150b9SStefan Roese	memory@00000000 {
64bf2150b9SStefan Roese		device_type = "memory";
65bf2150b9SStefan Roese		reg = <0x0 0x0 0x0 0x80000000>;
66bf2150b9SStefan Roese	};
67bf2150b9SStefan Roese};
68bf2150b9SStefan Roese
69bf2150b9SStefan Roese/* Accessible over the mini-USB CON9 connector on the main board */
70bf2150b9SStefan Roese&uart0 {
71bf2150b9SStefan Roese	status = "okay";
72bf2150b9SStefan Roese};
73bf2150b9SStefan Roese
74f99386c5SKonstantin Porotchkin&ap_pinctl {
75f99386c5SKonstantin Porotchkin	/* MPP Bus:
76f99386c5SKonstantin Porotchkin	 * SDIO  [0-10]
77f99386c5SKonstantin Porotchkin	 * UART0 [11,19]
78f99386c5SKonstantin Porotchkin	 */
79f99386c5SKonstantin Porotchkin		  /* 0 1 2 3 4 5 6 7 8 9 */
80f99386c5SKonstantin Porotchkin	pin-func = < 1 1 1 1 1 1 1 1 1 1
81f99386c5SKonstantin Porotchkin		     1 3 0 0 0 0 0 0 0 3 >;
82f99386c5SKonstantin Porotchkin};
83f99386c5SKonstantin Porotchkin
84*61dccf73SKonstantin Porotchkin&ap_sdhci0 {
85*61dccf73SKonstantin Porotchkin	pinctrl-names = "default";
86*61dccf73SKonstantin Porotchkin	pinctrl-0 = <&ap_emmc_pins>;
87*61dccf73SKonstantin Porotchkin	bus-width = <8>;
88*61dccf73SKonstantin Porotchkin	status = "okay";
89*61dccf73SKonstantin Porotchkin};
90*61dccf73SKonstantin Porotchkin
91f99386c5SKonstantin Porotchkin&cpm_pinctl {
92f99386c5SKonstantin Porotchkin	/* MPP Bus:
930f712f2cSKonstantin Porotchkin	 *	[0-31]	= 0xff: Keep default CP0_shared_pins
94f99386c5SKonstantin Porotchkin	 *	[11]	CLKOUT_MPP_11 (out)
95f99386c5SKonstantin Porotchkin	 *	[23]	LINK_RD_IN_CP2CP (in)
96f99386c5SKonstantin Porotchkin	 *	[25]	CLKOUT_MPP_25 (out)
97f99386c5SKonstantin Porotchkin	 *	[29]	AVS_FB_IN_CP2CP (in)
980f712f2cSKonstantin Porotchkin	 *	[32,34]	GE_MDIO/MDC
990f712f2cSKonstantin Porotchkin	 *	[33]	GPIO: GE_INT#/push button/Wake
1000f712f2cSKonstantin Porotchkin	 *	[35]	MSS_GPIO[3]: MSS_PWDN
1010f712f2cSKonstantin Porotchkin	 *	[36]	MSS_GPIO[5]: MSS_VTT_EN
1020f712f2cSKonstantin Porotchkin	 *	[37-38]	I2C0
1030f712f2cSKonstantin Porotchkin	 *	[39]	PTP_CLK
104f99386c5SKonstantin Porotchkin	 *	[40-41]	SATA[0/1]_PRESENT_ACTIVEn
1050f712f2cSKonstantin Porotchkin	 *	[42-43]	XG_MDC/XG_MDIO (XSMI)
106f99386c5SKonstantin Porotchkin	 *	[44-55]	RGMII1
107f99386c5SKonstantin Porotchkin	 *	[56-62]	SD
108f99386c5SKonstantin Porotchkin	 */
109f99386c5SKonstantin Porotchkin	/*   0    1    2    3    4    5    6    7    8    9 */
110f99386c5SKonstantin Porotchkin	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
111f99386c5SKonstantin Porotchkin		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
112f99386c5SKonstantin Porotchkin		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
1130f712f2cSKonstantin Porotchkin		     0xff 0xff 0x7  0x0  0x7  0xa  0xa  0x2  0x2  0x5
1140f712f2cSKonstantin Porotchkin		     0x9  0x9  0x8  0x8  0x1  0x1  0x1  0x1  0x1  0x1
1150f712f2cSKonstantin Porotchkin		     0x1  0x1  0x1  0x1  0x1  0x1  0xe  0xe  0xe  0xe
116f99386c5SKonstantin Porotchkin		     0xe  0xe  0xe>;
117f99386c5SKonstantin Porotchkin};
118bf2150b9SStefan Roese
1190f712f2cSKonstantin Porotchkin&cpm_comphy {
1200f712f2cSKonstantin Porotchkin	/* Serdes Configuration:
1210f712f2cSKonstantin Porotchkin	 *	Lane 0: PCIe0 (x1)
1220f712f2cSKonstantin Porotchkin	 *	Lane 1: SATA0
123cb686454SStefan Roese	 *	Lane 2: SFI (10G)
1240f712f2cSKonstantin Porotchkin	 *	Lane 3: SATA1
1250f712f2cSKonstantin Porotchkin	 *	Lane 4: USB3_HOST1
1260f712f2cSKonstantin Porotchkin	 *	Lane 5: PCIe2 (x1)
1270f712f2cSKonstantin Porotchkin	 */
1280f712f2cSKonstantin Porotchkin	phy0 {
1290f712f2cSKonstantin Porotchkin		phy-type = <PHY_TYPE_PEX0>;
1300f712f2cSKonstantin Porotchkin	};
1310f712f2cSKonstantin Porotchkin	phy1 {
1320f712f2cSKonstantin Porotchkin		phy-type = <PHY_TYPE_SATA0>;
1330f712f2cSKonstantin Porotchkin	};
1340f712f2cSKonstantin Porotchkin	phy2 {
135cb686454SStefan Roese		phy-type = <PHY_TYPE_SFI>;
1360f712f2cSKonstantin Porotchkin	};
1370f712f2cSKonstantin Porotchkin	phy3 {
1380f712f2cSKonstantin Porotchkin		phy-type = <PHY_TYPE_SATA1>;
1390f712f2cSKonstantin Porotchkin	};
1400f712f2cSKonstantin Porotchkin	phy4 {
1410f712f2cSKonstantin Porotchkin		phy-type = <PHY_TYPE_USB3_HOST1>;
1420f712f2cSKonstantin Porotchkin	};
1430f712f2cSKonstantin Porotchkin	phy5 {
1440f712f2cSKonstantin Porotchkin		phy-type = <PHY_TYPE_PEX2>;
1450f712f2cSKonstantin Porotchkin	};
1460f712f2cSKonstantin Porotchkin};
1470f712f2cSKonstantin Porotchkin
1480f712f2cSKonstantin Porotchkin/* CON6 on CP0 expansion */
1490f712f2cSKonstantin Porotchkin&cpm_pcie0 {
1500f712f2cSKonstantin Porotchkin	status = "okay";
1510f712f2cSKonstantin Porotchkin};
1520f712f2cSKonstantin Porotchkin
1530f712f2cSKonstantin Porotchkin&cpm_pcie1 {
1540f712f2cSKonstantin Porotchkin	status = "disabled";
1550f712f2cSKonstantin Porotchkin};
1560f712f2cSKonstantin Porotchkin
157bf2150b9SStefan Roese/* CON5 on CP0 expansion */
158bf2150b9SStefan Roese&cpm_pcie2 {
159bf2150b9SStefan Roese	status = "okay";
160bf2150b9SStefan Roese};
161bf2150b9SStefan Roese
162bf2150b9SStefan Roese&cpm_i2c0 {
163f99386c5SKonstantin Porotchkin	pinctrl-names = "default";
164f99386c5SKonstantin Porotchkin	pinctrl-0 = <&cpm_i2c0_pins>;
165bf2150b9SStefan Roese	status = "okay";
166bf2150b9SStefan Roese	clock-frequency = <100000>;
167bf2150b9SStefan Roese};
168bf2150b9SStefan Roese
169bf2150b9SStefan Roese/* CON4 on CP0 expansion */
170bf2150b9SStefan Roese&cpm_sata0 {
171bf2150b9SStefan Roese	status = "okay";
172bf2150b9SStefan Roese};
173bf2150b9SStefan Roese
174bf2150b9SStefan Roese/* CON9 on CP0 expansion */
175bf2150b9SStefan Roese&cpm_usb3_0 {
176bf2150b9SStefan Roese	status = "okay";
177bf2150b9SStefan Roese};
178bf2150b9SStefan Roese
179bf2150b9SStefan Roese/* CON10 on CP0 expansion */
180bf2150b9SStefan Roese&cpm_usb3_1 {
181bf2150b9SStefan Roese	status = "okay";
182bf2150b9SStefan Roese};
183bf2150b9SStefan Roese
1840f712f2cSKonstantin Porotchkin&cpm_utmi0 {
1850f712f2cSKonstantin Porotchkin	status = "okay";
1860f712f2cSKonstantin Porotchkin};
1870f712f2cSKonstantin Porotchkin
1880f712f2cSKonstantin Porotchkin&cpm_utmi1 {
1890f712f2cSKonstantin Porotchkin	status = "okay";
1900f712f2cSKonstantin Porotchkin};
1910f712f2cSKonstantin Porotchkin
192*61dccf73SKonstantin Porotchkin&cpm_sdhci0 {
193*61dccf73SKonstantin Porotchkin	pinctrl-names = "default";
194*61dccf73SKonstantin Porotchkin	pinctrl-0 = <&cpm_sdhci_pins>;
195*61dccf73SKonstantin Porotchkin	bus-width = <4>;
196*61dccf73SKonstantin Porotchkin	status = "okay";
197*61dccf73SKonstantin Porotchkin};
198*61dccf73SKonstantin Porotchkin
199f99386c5SKonstantin Porotchkin&cps_pinctl {
200f99386c5SKonstantin Porotchkin	/* MPP Bus:
201f99386c5SKonstantin Porotchkin	 *	[0-11]	RGMII0
202f99386c5SKonstantin Porotchkin	 *	[13-16]	SPI1
203f99386c5SKonstantin Porotchkin	 *	[27,31]	GE_MDIO/MDC
2040f712f2cSKonstantin Porotchkin	 *	[28]	SATA1_PRESENT_ACTIVEn
2050f712f2cSKonstantin Porotchkin	 *	[29-30]	UART0
2060f712f2cSKonstantin Porotchkin	 *	[32-62]	= 0xff: Keep default CP1_shared_pins
207f99386c5SKonstantin Porotchkin	 */
208f99386c5SKonstantin Porotchkin	/*   0    1    2    3    4    5    6    7    8    9 */
209f99386c5SKonstantin Porotchkin	pin-func = < 0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3
2100f712f2cSKonstantin Porotchkin		     0x3  0x3  0x3  0x3  0x3  0x3  0x3  0xff 0xff 0xff
2110f712f2cSKonstantin Porotchkin		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8  0x9  0xa
2120f712f2cSKonstantin Porotchkin		     0xA  0x8  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
213f99386c5SKonstantin Porotchkin		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
214f99386c5SKonstantin Porotchkin		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
215f99386c5SKonstantin Porotchkin		     0xff 0xff 0xff>;
216f99386c5SKonstantin Porotchkin};
217f99386c5SKonstantin Porotchkin
2180f712f2cSKonstantin Porotchkin&cps_comphy {
2190f712f2cSKonstantin Porotchkin	/* Serdes Configuration:
2200f712f2cSKonstantin Porotchkin	 *	Lane 0: PCIe0 (x1)
2210f712f2cSKonstantin Porotchkin	 *	Lane 1: SATA0
222cb686454SStefan Roese	 *	Lane 2: SFI (10G)
2230f712f2cSKonstantin Porotchkin	 *	Lane 3: SATA1
2240f712f2cSKonstantin Porotchkin	 *	Lane 4: PCIe1 (x1)
2250f712f2cSKonstantin Porotchkin	 *	Lane 5: PCIe2 (x1)
2260f712f2cSKonstantin Porotchkin	 */
2270f712f2cSKonstantin Porotchkin	phy0 {
2280f712f2cSKonstantin Porotchkin		phy-type = <PHY_TYPE_PEX0>;
2290f712f2cSKonstantin Porotchkin	};
2300f712f2cSKonstantin Porotchkin	phy1 {
2310f712f2cSKonstantin Porotchkin		phy-type = <PHY_TYPE_SATA0>;
2320f712f2cSKonstantin Porotchkin	};
2330f712f2cSKonstantin Porotchkin	phy2 {
234cb686454SStefan Roese		phy-type = <PHY_TYPE_SFI>;
2350f712f2cSKonstantin Porotchkin	};
2360f712f2cSKonstantin Porotchkin	phy3 {
2370f712f2cSKonstantin Porotchkin		phy-type = <PHY_TYPE_SATA1>;
2380f712f2cSKonstantin Porotchkin	};
2390f712f2cSKonstantin Porotchkin	phy4 {
2400f712f2cSKonstantin Porotchkin		phy-type = <PHY_TYPE_PEX1>;
2410f712f2cSKonstantin Porotchkin	};
2420f712f2cSKonstantin Porotchkin	phy5 {
2430f712f2cSKonstantin Porotchkin		phy-type = <PHY_TYPE_PEX2>;
2440f712f2cSKonstantin Porotchkin	};
2450f712f2cSKonstantin Porotchkin};
2460f712f2cSKonstantin Porotchkin
2470f712f2cSKonstantin Porotchkin/* CON6 on CP1 expansion */
2480f712f2cSKonstantin Porotchkin&cps_pcie0 {
2490f712f2cSKonstantin Porotchkin	status = "okay";
2500f712f2cSKonstantin Porotchkin};
2510f712f2cSKonstantin Porotchkin
2520f712f2cSKonstantin Porotchkin&cps_pcie1 {
2530f712f2cSKonstantin Porotchkin	status = "okay";
2540f712f2cSKonstantin Porotchkin};
2550f712f2cSKonstantin Porotchkin
256bf2150b9SStefan Roese/* CON5 on CP1 expansion */
257bf2150b9SStefan Roese&cps_pcie2 {
258bf2150b9SStefan Roese	status = "okay";
259bf2150b9SStefan Roese};
260bf2150b9SStefan Roese
2615b613d38SKonstantin Porotchkin&cps_spi1 {
262f99386c5SKonstantin Porotchkin	pinctrl-names = "default";
263f99386c5SKonstantin Porotchkin	pinctrl-0 = <&cps_spi1_pins>;
264bf2150b9SStefan Roese	status = "okay";
2655b613d38SKonstantin Porotchkin
2665b613d38SKonstantin Porotchkin	spi-flash@0 {
2675b613d38SKonstantin Porotchkin		#address-cells = <1>;
2685b613d38SKonstantin Porotchkin		#size-cells = <1>;
2695b613d38SKonstantin Porotchkin		compatible = "jedec,spi-nor";
2705b613d38SKonstantin Porotchkin		reg = <0>;
2715b613d38SKonstantin Porotchkin		spi-max-frequency = <10000000>;
2725b613d38SKonstantin Porotchkin
2735b613d38SKonstantin Porotchkin		partitions {
2745b613d38SKonstantin Porotchkin			compatible = "fixed-partitions";
2755b613d38SKonstantin Porotchkin			#address-cells = <1>;
2765b613d38SKonstantin Porotchkin			#size-cells = <1>;
2775b613d38SKonstantin Porotchkin
2785b613d38SKonstantin Porotchkin			partition@0 {
2795b613d38SKonstantin Porotchkin				label = "U-Boot";
2805b613d38SKonstantin Porotchkin				reg = <0 0x200000>;
2815b613d38SKonstantin Porotchkin			};
2825b613d38SKonstantin Porotchkin			partition@400000 {
2835b613d38SKonstantin Porotchkin				label = "Filesystem";
2845b613d38SKonstantin Porotchkin				reg = <0x200000 0xce0000>;
2855b613d38SKonstantin Porotchkin			};
2865b613d38SKonstantin Porotchkin		};
2875b613d38SKonstantin Porotchkin	};
288bf2150b9SStefan Roese};
289bf2150b9SStefan Roese
290bf2150b9SStefan Roese/* CON4 on CP1 expansion */
291bf2150b9SStefan Roese&cps_sata0 {
292bf2150b9SStefan Roese	status = "okay";
293bf2150b9SStefan Roese};
294bf2150b9SStefan Roese
295bf2150b9SStefan Roese/* CON9 on CP1 expansion */
296bf2150b9SStefan Roese&cps_usb3_0 {
297bf2150b9SStefan Roese	status = "okay";
298bf2150b9SStefan Roese};
299bf2150b9SStefan Roese
300bf2150b9SStefan Roese/* CON10 on CP1 expansion */
301bf2150b9SStefan Roese&cps_usb3_1 {
302bf2150b9SStefan Roese	status = "okay";
303bf2150b9SStefan Roese};
30492fdaf0cSStefan Roese
30592fdaf0cSStefan Roese&cps_utmi0 {
30692fdaf0cSStefan Roese	status = "okay";
30792fdaf0cSStefan Roese};
308a6555ebeSThomas Petazzoni
309a6555ebeSThomas Petazzoni&cpm_mdio {
310a6555ebeSThomas Petazzoni	phy1: ethernet-phy@1 {
311a6555ebeSThomas Petazzoni		reg = <1>;
312a6555ebeSThomas Petazzoni	};
313a6555ebeSThomas Petazzoni};
314a6555ebeSThomas Petazzoni
315a6555ebeSThomas Petazzoni&cpm_ethernet {
316a6555ebeSThomas Petazzoni	status = "okay";
317a6555ebeSThomas Petazzoni};
318a6555ebeSThomas Petazzoni
319a6555ebeSThomas Petazzoni&cpm_eth2 {
320a6555ebeSThomas Petazzoni	status = "okay";
321a6555ebeSThomas Petazzoni	phy = <&phy1>;
322a6555ebeSThomas Petazzoni	phy-mode = "rgmii-id";
323a6555ebeSThomas Petazzoni};
324