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/openbmc/linux/drivers/i2c/muxes/
H A Di2c-mux-gpmux.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/i2c-mux.h>
18 struct mux_control *control; member
28 ret = mux_control_select(mux->control, chan); in i2c_mux_select()
29 mux->do_not_deselect = ret < 0; in i2c_mux_select()
38 if (mux->do_not_deselect) in i2c_mux_deselect()
41 return mux_control_deselect(mux->control); in i2c_mux_deselect()
46 struct device_node *np = dev->of_node; in mux_parent_adapter()
48 struct i2c_adapter *parent; in mux_parent_adapter() local
50 parent_np = of_parse_phandle(np, "i2c-parent", 0); in mux_parent_adapter()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dnxp,sc16is7xx.txt1 * NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART)
5 - compatible: Should be one of the following:
6 - "nxp,sc16is740" for NXP SC16IS740,
7 - "nxp,sc16is741" for NXP SC16IS741,
8 - "nxp,sc16is750" for NXP SC16IS750,
9 - "nxp,sc16is752" for NXP SC16IS752,
10 - "nxp,sc16is760" for NXP SC16IS760,
11 - "nxp,sc16is762" for NXP SC16IS762.
12 - reg: I2C address of the SC16IS7xx device.
13 - interrupts: Should contain the UART interrupt
[all …]
/openbmc/linux/drivers/iio/multiplexer/
H A Diio-mux.c1 // SPDX-License-Identifier: GPL-2.0
31 struct mux_control *control; member
32 struct iio_channel *parent; member
42 struct mux_child *child = &mux->child[idx]; in iio_mux_select()
43 struct iio_chan_spec const *chan = &mux->chan[idx]; in iio_mux_select()
47 ret = mux_control_select_delay(mux->control, chan->channel, in iio_mux_select()
48 mux->delay_us); in iio_mux_select()
50 mux->cached_state = -1; in iio_mux_select()
54 if (mux->cached_state == chan->channel) in iio_mux_select()
57 if (chan->ext_info) { in iio_mux_select()
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/openbmc/linux/Documentation/devicetree/bindings/mux/
H A Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
13 Define register bitfields to be used to control multiplexers. The parent
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
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/openbmc/linux/include/linux/
H A Dwwan.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 * enum wwan_port_type - WWAN port types
14 * @WWAN_PORT_MBIM: Mobile Broadband Interface Model control
15 * @WWAN_PORT_QMI: Qcom modem/MSM interface for modem control
18 * @WWAN_PORT_XMMRPC: Control protocol for Intel XMM modems
35 WWAN_PORT_MAX = __WWAN_PORT_MAX - 1,
45 /** struct wwan_port_ops - The WWAN port operations
48 * @tx: Non-blocking routine that sends WWAN port protocol data to the device.
53 * The wwan_port_ops structure contains a list of low-level operations
54 * that control a WWAN port device. All functions are mandatory unless specified.
[all …]
H A Dpowercap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
24 * struct powercap_control_type_ops - Define control type callbacks
25 * @set_enable: Enable/Disable whole control type.
32 * control type is closed. So it is safe to free data
33 * structure associated with this control type.
35 * for the control type.
37 * This structure defines control type callbacks to be implemented by client
47 * struct powercap_control_type - Defines a powercap control_type
52 * @lock: mutex for control type
58 * @node: linked-list node
[all …]
/openbmc/linux/drivers/usb/musb/
H A Dsunxi.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/phy/phy-sun4i-usb.h>
102 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) in sunxi_musb_work()
105 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) { in sunxi_musb_work()
106 struct musb *musb = glue->musb; in sunxi_musb_work()
110 spin_lock_irqsave(&musb->lock, flags); in sunxi_musb_work()
112 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL); in sunxi_musb_work()
113 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) { in sunxi_musb_work()
114 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); in sunxi_musb_work()
115 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; in sunxi_musb_work()
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H A Dmusb_dsps.c1 // SPDX-License-Identifier: GPL-2.0
21 #include <linux/dma-mapping.h>
25 #include <linux/platform_data/usb-omap.h>
45 u16 control; member
58 /* bit positions for control */
89 u32 control; member
117 { "control", 0x14 },
135 struct musb *musb = platform_get_drvdata(glue->musb); in dsps_mod_timer()
139 wait = msecs_to_jiffies(glue->wrp->poll_timeout); in dsps_mod_timer()
143 mod_timer(&musb->dev_timer, jiffies + wait); in dsps_mod_timer()
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/openbmc/linux/include/linux/firmware/imx/svc/
H A Dpm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2017-2018 NXP
8 * control, clock control, reset control, and wake-up event control.
56 #define IMX_SC_PM_PW_MODE_LP 2 /* Power in low-power */
77 * Defines for SC PM CLK Parent
79 #define IMX_SC_PM_PARENT_XTAL 0 /* Parent is XTAL. */
80 #define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */
81 #define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */
82 #define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */
83 #define IMX_SC_PM_PARENT_BYPS 4 /* Parent is a bypass clock. */
/openbmc/linux/drivers/acpi/acpica/
H A Dpsparse.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: psparse - Parser top level AML parse routines
6 * Copyright (C) 2000 - 2023, Intel Corp.
34 * PARAMETERS: opcode - An AML opcode
44 /* Extended (2-byte) opcode if > 255 */ in acpi_ps_get_opcode_size()
59 * PARAMETERS: parser_state - A parser state object
72 aml = parser_state->aml; in acpi_ps_peek_opcode()
90 * PARAMETERS: walk_state - Current State
91 * op - Op to complete
121 if (((walk_state->parse_flags & ACPI_PARSE_TREE_MASK) != in acpi_ps_complete_this_op()
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/openbmc/qemu/include/hw/misc/
H A Dnpcm7xx_clk.h2 * Nuvoton NPCM7xx Clock Control Registers.
29 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
86 * struct NPCM7xxClockPLLState - A PLL module in CLK module.
91 * @reg: The control registers for this PLL module.
94 DeviceState parent; member
105 * struct NPCM7xxClockSELState - A SEL module in CLK module.
111 * @offset: The offset of this module in the control register.
112 * @len: The length of this module in the control register.
115 DeviceState parent; member
128 * struct NPCM7xxClockDividerState - A Divider module in CLK module.
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/openbmc/linux/drivers/infiniband/hw/qib/
H A Dqib_pcie.c2 * Copyright (c) 2010 - 2017 Intel Corporation. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
50 * from qib_pcie_params, which every chip-specific
81 qib_early_err(&pdev->dev, "pci enable failed: error %d\n", in qib_pcie_init()
82 -ret); in qib_pcie_init()
88 qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret); in qib_pcie_init()
92 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in qib_pcie_init()
99 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in qib_pcie_init()
118 * fields required to re-initialize after a chip reset, or for
[all …]
/openbmc/linux/drivers/regulator/
H A Dtps65090-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * struct tps65090_regulator - Per-regulator data for a tps65090 regulator
54 * tps65090_reg_set_overcurrent_wait - Setup overcurrent wait
62 * Return: 0 if no error, non-zero if there was an error writing the register.
69 ret = regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in tps65090_reg_set_overcurrent_wait()
71 ri->overcurrent_wait << CTRL_WT_BIT); in tps65090_reg_set_overcurrent_wait()
73 dev_err(&rdev->dev, "Error updating overcurrent wait %#x\n", in tps65090_reg_set_overcurrent_wait()
74 rdev->desc->enable_reg); in tps65090_reg_set_overcurrent_wait()
81 * tps65090_try_enable_fet - Try to enable a FET
85 * Return: 0 if ok, -ENOTRECOVERABLE if the FET power good bit did not get
[all …]
/openbmc/linux/drivers/hid/
H A Dhid-roccat-koneplus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 * and functionality and without the non-standard behaviours the Kone had.
22 #include <linux/hid-roccat.h>
23 #include "hid-ids.h"
24 #include "hid-roccat-common.h"
25 #include "hid-roccat-koneplus.h"
32 koneplus->actual_profile = new_profile; in koneplus_profile_activated()
38 struct roccat_common2_control control; in koneplus_send_control() local
43 return -EINVAL; in koneplus_send_control()
45 control.command = ROCCAT_COMMON_COMMAND_CONTROL; in koneplus_send_control()
[all …]
H A Dhid-roccat-kovaplus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/hid-roccat.h>
21 #include "hid-ids.h"
22 #include "hid-roccat-common.h"
23 #include "hid-roccat-kovaplus.h"
35 if (new_profile_index >= ARRAY_SIZE(kovaplus->profile_settings)) in kovaplus_profile_activated()
37 kovaplus->actual_profile = new_profile_index; in kovaplus_profile_activated()
38 kovaplus->actual_cpi = kovaplus->profile_settings[new_profile_index].cpi_startup_level; in kovaplus_profile_activated()
39 kovaplus->actual_x_sensitivity = kovaplus->profile_settings[new_profile_index].sensitivity_x; in kovaplus_profile_activated()
40 kovaplus->actual_y_sensitivity = kovaplus->profile_settings[new_profile_index].sensitivity_y; in kovaplus_profile_activated()
[all …]
H A Dhid-roccat-pyra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #include <linux/hid-roccat.h>
23 #include "hid-ids.h"
24 #include "hid-roccat-common.h"
25 #include "hid-roccat-pyra.h"
32 if (new_profile >= ARRAY_SIZE(pyra->profile_settings)) in profile_activated()
34 pyra->actual_profile = new_profile; in profile_activated()
35 pyra->actual_cpi = pyra->profile_settings[pyra->actual_profile].y_cpi; in profile_activated()
41 struct roccat_common2_control control; in pyra_send_control() local
46 return -EINVAL; in pyra_send_control()
[all …]
/openbmc/qemu/hw/arm/
H A Dbcm2836.c9 * See the COPYING file in the top-level directory.
18 #include "target/arm/cpu-qom.h"
22 DEFINE_PROP_UINT32("enabled-cpus", BCM283XBaseState, enabled_cpus, 0);
30 for (n = 0; n < bc->core_count; n++) { in bcm283x_base_init()
31 object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, in bcm283x_base_init()
32 bc->cpu_type); in bcm283x_base_init()
34 if (bc->core_count > 1) { in bcm283x_base_init()
36 qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count); in bcm283x_base_init()
39 if (bc->ctrl_base) { in bcm283x_base_init()
40 object_initialize_child(obj, "control", &s->control, in bcm283x_base_init()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h1 /* SPDX-License-Identifier: GPL-2.0+ */
37 * struct clk_ops - standard clock operations
42 * @set_parent: set the clock's parent, see clk_set_parent().
54 int (*set_parent)(struct clk *c, struct clk *parent);
58 struct clk *parent; member
63 /* programmable divider. 0 means fixed ratio to parent clock */
75 /* The common clock framework uses u8 to represent a parent index */
79 #define BAD_CLK_NAME ((const char *)-1)
88 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
89 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
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/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h1 /* SPDX-License-Identifier: GPL-2.0+ */
37 * struct clk_ops - standard clock operations
42 * @set_parent: set the clock's parent, see clk_set_parent().
54 int (*set_parent) (struct clk *c, struct clk *parent);
58 struct clk *parent; member
63 /* programmable divider. 0 means fixed ratio to parent clock */
75 /* The common clock framework uses u8 to represent a parent index */
79 #define BAD_CLK_NAME ((const char *)-1)
88 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
89 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
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/openbmc/linux/drivers/clk/bcm/
H A Dclk-kona-setup.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "clk-kona.h"
13 #define selector_clear_exists(sel) ((sel)->width = 0)
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
33 pr_err("%s: bad policy control offset for %s " in ccu_data_offsets_valid()
35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
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/openbmc/qemu/hw/i2c/
H A Di2c_mux_pca954x.c22 #include "hw/qdev-core.h"
23 #include "hw/qdev-properties.h"
35 * struct Pca954xState - The pca954x state object.
36 * @control: The value written to the mux control.
41 SMBusDevice parent; member
43 uint8_t control; member
52 * struct Pca954xClass - The pca954x class object.
56 SMBusDeviceClass parent; member
76 if ((candidate->address == address) || broadcast) { in OBJECT_DECLARE_TYPE()
78 node->elt = candidate; in OBJECT_DECLARE_TYPE()
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/openbmc/linux/drivers/irqchip/
H A Dirq-al-fic.c1 // SPDX-License-Identifier: GPL-2.0
49 u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL); in al_fic_set_trigger() local
53 control &= ~CONTROL_TRIGGER_RISING; in al_fic_set_trigger()
56 control |= CONTROL_TRIGGER_RISING; in al_fic_set_trigger()
58 gc->chip_types->handler = handler; in al_fic_set_trigger()
59 fic->state = new_state; in al_fic_set_trigger()
60 writel_relaxed(control, fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
66 struct al_fic *fic = gc->private; in al_fic_irq_set_type()
75 ret = -EINVAL; in al_fic_irq_set_type()
91 if (fic->state == AL_FIC_UNCONFIGURED) { in al_fic_irq_set_type()
[all …]
/openbmc/qemu/hw/timer/
H A Dcmsdk-apb-dualtimer.c2 * ARM CMSDK APB dual-timer emulation
13 * This is a model of the "APB dual-input timer" which is part of the Cortex-M
14 * System Design Kit (CMSDK) and documented in the Cortex-M System
16 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
26 #include "hw/qdev-properties.h"
28 #include "hw/qdev-clock.h"
29 #include "hw/timer/cmsdk-apb-dualtimer.h"
35 FIELD(CONTROL, ONESHOT, 0, 1)
36 FIELD(CONTROL, SIZE, 1, 1)
37 FIELD(CONTROL, PRESCALE, 2, 2)
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/openbmc/linux/drivers/usb/common/
H A Dulpi.c1 // SPDX-License-Identifier: GPL-2.0
3 * ulpi.c - USB ULPI PHY bus
19 #include <linux/clk/clk-conf.h>
21 /* -------------------------------------------------------------------------- */
25 return ulpi->ops->read(ulpi->dev.parent, addr); in ulpi_read()
31 return ulpi->ops->write(ulpi->dev.parent, addr, val); in ulpi_write()
35 /* -------------------------------------------------------------------------- */
47 if (ulpi->id.vendor == 0 || !drv->id_table) in ulpi_match()
50 for (id = drv->id_table; id->vendor; id++) in ulpi_match()
51 if (id->vendor == ulpi->id.vendor && in ulpi_match()
[all …]
/openbmc/u-boot/drivers/spi/
H A Daltera_spi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (c) 2005-2008 Analog Devices Inc.
28 u32 control; member
43 struct udevice *bus = dev->parent; in spi_cs_activate()
45 struct altera_spi_regs *const regs = priv->regs; in spi_cs_activate()
47 writel(1 << cs, &regs->slave_sel); in spi_cs_activate()
48 writel(ALTERA_SPI_CONTROL_SSO_MSK, &regs->control); in spi_cs_activate()
53 struct udevice *bus = dev->parent; in spi_cs_deactivate()
55 struct altera_spi_regs *const regs = priv->regs; in spi_cs_deactivate()
57 writel(0, &regs->control); in spi_cs_deactivate()
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