189054c7bSJon Ringle* NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART) 28f4a9120SRama Kiran Kumar Indrakanti* i2c as bus 389054c7bSJon Ringle 489054c7bSJon RingleRequired properties: 589054c7bSJon Ringle- compatible: Should be one of the following: 689054c7bSJon Ringle - "nxp,sc16is740" for NXP SC16IS740, 789054c7bSJon Ringle - "nxp,sc16is741" for NXP SC16IS741, 889054c7bSJon Ringle - "nxp,sc16is750" for NXP SC16IS750, 989054c7bSJon Ringle - "nxp,sc16is752" for NXP SC16IS752, 1089054c7bSJon Ringle - "nxp,sc16is760" for NXP SC16IS760, 1189054c7bSJon Ringle - "nxp,sc16is762" for NXP SC16IS762. 1289054c7bSJon Ringle- reg: I2C address of the SC16IS7xx device. 1389054c7bSJon Ringle- interrupts: Should contain the UART interrupt 1489054c7bSJon Ringle- clocks: Reference to the IC source clock. 158650e026SAndy Shevchenko OR (when there is no clock provider visible to the platform) 168650e026SAndy Shevchenko- clock-frequency: The source clock frequency for the IC. 1789054c7bSJon Ringle 1889054c7bSJon RingleOptional properties: 1989054c7bSJon Ringle- gpio-controller: Marks the device node as a GPIO controller. 2089054c7bSJon Ringle- #gpio-cells: Should be two. The first cell is the GPIO number and 2189054c7bSJon Ringle the second cell is used to specify the GPIO polarity: 2289054c7bSJon Ringle 0 = active high, 2389054c7bSJon Ringle 1 = active low. 244a9b984fSPascal Huerst- irda-mode-ports: An array that lists the indices of the port that 254a9b984fSPascal Huerst should operate in IrDA mode. 26*4cf478dcSHugo Villeneuve- nxp,modem-control-line-ports: An array that lists the indices of the port that 27*4cf478dcSHugo Villeneuve should have shared GPIO lines configured as 28*4cf478dcSHugo Villeneuve modem control lines. 2989054c7bSJon Ringle 3089054c7bSJon RingleExample: 3189054c7bSJon Ringle sc16is750: sc16is750@51 { 3289054c7bSJon Ringle compatible = "nxp,sc16is750"; 3389054c7bSJon Ringle reg = <0x51>; 3489054c7bSJon Ringle clocks = <&clk20m>; 3589054c7bSJon Ringle interrupt-parent = <&gpio3>; 3689054c7bSJon Ringle interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 3789054c7bSJon Ringle gpio-controller; 3889054c7bSJon Ringle #gpio-cells = <2>; 3989054c7bSJon Ringle }; 408f4a9120SRama Kiran Kumar Indrakanti 41*4cf478dcSHugo Villeneuve sc16is752: sc16is752@53 { 42*4cf478dcSHugo Villeneuve compatible = "nxp,sc16is752"; 43*4cf478dcSHugo Villeneuve reg = <0x53>; 44*4cf478dcSHugo Villeneuve clocks = <&clk20m>; 45*4cf478dcSHugo Villeneuve interrupt-parent = <&gpio3>; 46*4cf478dcSHugo Villeneuve interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 47*4cf478dcSHugo Villeneuve nxp,modem-control-line-ports = <1>; /* Port 1 as modem control lines */ 48*4cf478dcSHugo Villeneuve gpio-controller; /* Port 0 as GPIOs */ 49*4cf478dcSHugo Villeneuve #gpio-cells = <2>; 50*4cf478dcSHugo Villeneuve }; 51*4cf478dcSHugo Villeneuve 52*4cf478dcSHugo Villeneuve sc16is752: sc16is752@54 { 53*4cf478dcSHugo Villeneuve compatible = "nxp,sc16is752"; 54*4cf478dcSHugo Villeneuve reg = <0x54>; 55*4cf478dcSHugo Villeneuve clocks = <&clk20m>; 56*4cf478dcSHugo Villeneuve interrupt-parent = <&gpio3>; 57*4cf478dcSHugo Villeneuve interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 58*4cf478dcSHugo Villeneuve nxp,modem-control-line-ports = <0 1>; /* Ports 0 and 1 as modem control lines */ 59*4cf478dcSHugo Villeneuve }; 60*4cf478dcSHugo Villeneuve 618f4a9120SRama Kiran Kumar Indrakanti* spi as bus 628f4a9120SRama Kiran Kumar Indrakanti 638f4a9120SRama Kiran Kumar IndrakantiRequired properties: 648f4a9120SRama Kiran Kumar Indrakanti- compatible: Should be one of the following: 658f4a9120SRama Kiran Kumar Indrakanti - "nxp,sc16is740" for NXP SC16IS740, 668f4a9120SRama Kiran Kumar Indrakanti - "nxp,sc16is741" for NXP SC16IS741, 678f4a9120SRama Kiran Kumar Indrakanti - "nxp,sc16is750" for NXP SC16IS750, 688f4a9120SRama Kiran Kumar Indrakanti - "nxp,sc16is752" for NXP SC16IS752, 698f4a9120SRama Kiran Kumar Indrakanti - "nxp,sc16is760" for NXP SC16IS760, 708f4a9120SRama Kiran Kumar Indrakanti - "nxp,sc16is762" for NXP SC16IS762. 718f4a9120SRama Kiran Kumar Indrakanti- reg: SPI chip select number. 728f4a9120SRama Kiran Kumar Indrakanti- interrupts: Specifies the interrupt source of the parent interrupt 738f4a9120SRama Kiran Kumar Indrakanti controller. The format of the interrupt specifier depends on the 748f4a9120SRama Kiran Kumar Indrakanti parent interrupt controller. 758f4a9120SRama Kiran Kumar Indrakanti- clocks: phandle to the IC source clock. 768f4a9120SRama Kiran Kumar Indrakanti 778f4a9120SRama Kiran Kumar IndrakantiOptional properties: 788f4a9120SRama Kiran Kumar Indrakanti- gpio-controller: Marks the device node as a GPIO controller. 798f4a9120SRama Kiran Kumar Indrakanti- #gpio-cells: Should be two. The first cell is the GPIO number and 808f4a9120SRama Kiran Kumar Indrakanti the second cell is used to specify the GPIO polarity: 818f4a9120SRama Kiran Kumar Indrakanti 0 = active high, 828f4a9120SRama Kiran Kumar Indrakanti 1 = active low. 834a9b984fSPascal Huerst- irda-mode-ports: An array that lists the indices of the port that 844a9b984fSPascal Huerst should operate in IrDA mode. 85*4cf478dcSHugo Villeneuve- nxp,modem-control-line-ports: An array that lists the indices of the port that 86*4cf478dcSHugo Villeneuve should have shared GPIO lines configured as 87*4cf478dcSHugo Villeneuve modem control lines. 888f4a9120SRama Kiran Kumar Indrakanti 898f4a9120SRama Kiran Kumar IndrakantiExample: 908f4a9120SRama Kiran Kumar Indrakanti sc16is750: sc16is750@0 { 918f4a9120SRama Kiran Kumar Indrakanti compatible = "nxp,sc16is750"; 928f4a9120SRama Kiran Kumar Indrakanti reg = <0>; 938f4a9120SRama Kiran Kumar Indrakanti clocks = <&clk20m>; 948f4a9120SRama Kiran Kumar Indrakanti interrupt-parent = <&gpio3>; 958f4a9120SRama Kiran Kumar Indrakanti interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 968f4a9120SRama Kiran Kumar Indrakanti gpio-controller; 978f4a9120SRama Kiran Kumar Indrakanti #gpio-cells = <2>; 988f4a9120SRama Kiran Kumar Indrakanti }; 99*4cf478dcSHugo Villeneuve 100*4cf478dcSHugo Villeneuve sc16is752: sc16is752@1 { 101*4cf478dcSHugo Villeneuve compatible = "nxp,sc16is752"; 102*4cf478dcSHugo Villeneuve reg = <1>; 103*4cf478dcSHugo Villeneuve clocks = <&clk20m>; 104*4cf478dcSHugo Villeneuve interrupt-parent = <&gpio3>; 105*4cf478dcSHugo Villeneuve interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 106*4cf478dcSHugo Villeneuve nxp,modem-control-line-ports = <1>; /* Port 1 as modem control lines */ 107*4cf478dcSHugo Villeneuve gpio-controller; /* Port 0 as GPIOs */ 108*4cf478dcSHugo Villeneuve #gpio-cells = <2>; 109*4cf478dcSHugo Villeneuve }; 110*4cf478dcSHugo Villeneuve 111*4cf478dcSHugo Villeneuve sc16is752: sc16is752@2 { 112*4cf478dcSHugo Villeneuve compatible = "nxp,sc16is752"; 113*4cf478dcSHugo Villeneuve reg = <2>; 114*4cf478dcSHugo Villeneuve clocks = <&clk20m>; 115*4cf478dcSHugo Villeneuve interrupt-parent = <&gpio3>; 116*4cf478dcSHugo Villeneuve interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 117*4cf478dcSHugo Villeneuve nxp,modem-control-line-ports = <0 1>; /* Ports 0 and 1 as modem control lines */ 118*4cf478dcSHugo Villeneuve }; 119