| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | renesas,ceu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/renesas,ceu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Capture Engine Unit (CEU)
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - linux-renesas-soc@vger.kernel.org
15 Mobile, R-Mobile and RZ SoCs. The interface supports a single parallel input
21 - renesas,r7s72100-ceu
22 - renesas,r8a7740-ceu
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| /openbmc/linux/arch/sh/boards/mach-ap325rxa/ |
| H A D | setup.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas - AP-325RXA
4 * (Compatible with Algo System ., LTD. - AP-320A)
10 #include <asm/clock.h>
16 #include <linux/dma-map-ops.h>
38 #include <media/drv-intf/renesas-ceu.h>
74 .id = -1,
83 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
91 .mask_flags = MTD_WRITEABLE, /* Read-only */
97 .name = "free-area0",
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| /openbmc/linux/arch/sh/boards/mach-migor/ |
| H A D | setup.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas System Solutions Asia Pte. Ltd - Migo-R
8 #include <linux/dma-map-ops.h>
30 #include <media/drv-intf/renesas-ceu.h>
33 #include <asm/clock.h>
78 .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
104 .id = 0, /* "keysc0" clock */
118 .mask_flags = MTD_WRITEABLE, /* Read-only */
148 .name = "physmap-flash",
176 writeb(cmd, chip->legacy.IO_ADDR_W + 0x00400000); in migor_nand_flash_cmd_ctl()
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| /openbmc/linux/arch/sh/boards/mach-kfr2r09/ |
| H A D | setup.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <asm/clock.h>
35 #include <linux/dma-map-ops.h>
39 #include <media/drv-intf/renesas-ceu.h>
47 /* set VIO_CKO clock to 25MHz */
57 .mask_flags = MTD_WRITEABLE, /* Read-only */
82 .name = "physmap-flash",
100 .name = "onenand-flash",
106 .mode = SH_KEYSC_MODE_1, /* KEYOUT0->4, KEYIN0->4 */
134 .id = 0, /* "keysc0" clock */
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| /openbmc/linux/arch/arm/boot/dts/renesas/ |
| H A D | gr-peach-audiocamerashield.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the GR-Peach audiocamera shield expansion board
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
13 /* On-board camera clock. */
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <27000000>;
28 /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */
44 pinctrl-names = "default";
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| H A D | r8a7740.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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| H A D | r7s72100.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-14 Renesas Solutions Corp.
6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
9 #include <dt-bindings/clock/r7s72100-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
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| H A D | r7s9210-rza2mevb.dts | 1 // SPDX-License-Identifier: GPL-2.0
8 * Hence the 64 MiB of SDRAM on the sub-board needs to be enabled, which has
10 * - SCIF4 connected to the on-board USB-serial can no longer be used as the
12 * - Instead, SCIF2 is used as the serial console, by connecting a 3.3V TTL
13 * USB-to-Serial adapter to the CMOS camera connector:
14 * - RXD = CN17-9,
15 * - TXD = CN17-10,
16 * - GND = CN17-2 or CN17-17,
17 * - The first Ethernet channel can no longer be used,
18 * - USB Channel 1 loses the overcurrent input signal.
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| /openbmc/linux/arch/sh/boards/mach-se/7724/ |
| H A D | setup.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <asm/clock.h>
35 #include <linux/dma-map-ops.h>
37 #include <mach-se/mach/se7724.h>
38 #include <media/drv-intf/renesas-ceu.h>
51 * ------------------------------------
55 * SW41 : abxx xxxx -> a = 0 : Analog monitor
65 * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
73 * Please change J20, J21, J22 pin to 1-2 connection.
85 .id = -1,
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| /openbmc/linux/arch/sh/boards/mach-ecovec24/ |
| H A D | setup.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <asm/clock.h>
39 #include <linux/dma-map-ops.h>
41 #include <media/drv-intf/renesas-ceu.h>
52 *-----------------------------------------
62 *------------------------------
69 * DS2[5] = NTSC_OUT Clock ON : On board OSC
71 * DS2[6-7] = MMC / SD ON-OFF : SD
72 * OFF-ON : MMC
76 * FSI - DA7210
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| /openbmc/linux/arch/sh/kernel/cpu/sh4a/ |
| H A D | clock-sh7724.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
5 * SH7724 clock framework support
15 #include <asm/clock.h>
33 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
39 * Default rate for the root input clock, reset this with clk_set_rate()
58 return (clk->parent->rate * mult) / div; in fll_recalc()
78 return clk->parent->rate * mult; in pll_recalc()
90 /* A fixed divide-by-3 block use by the div6 clocks */
93 return clk->parent->rate / 3; in div3_recalc()
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| H A D | clock-sh7722.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
5 * SH7722 clock framework support
14 #include <asm/clock.h>
29 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
35 * Default rate for the root input clock, reset this with clk_set_rate()
52 return clk->parent->rate * mult; in dll_recalc()
75 return (clk->parent->rate * mult) / div; in pll_recalc()
194 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[HWBLK_TMU]),
196 CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &mstp_clks[HWBLK_CMT]),
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| H A D | clock-sh7723.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4a/clock-sh7723.c
5 * SH7723 clock framework support
15 #include <asm/clock.h>
30 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
36 * Default rate for the root input clock, reset this with clk_set_rate()
53 return clk->parent->rate * mult; in dll_recalc()
76 return (clk->parent->rate * mult) / div; in pll_recalc()
142 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
223 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
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| /openbmc/linux/arch/sh/include/cpu-sh4/cpu/ |
| H A D | sh7722.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * MD0: CPG - Clock Mode 0->3
8 * MD1: CPG - Clock Mode 0->3
9 * MD2: CPG - Reserved (L: Normal operation)
10 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
11 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
16 * GPIO_FN_xx - GPIO used to select pin function
17 * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
121 /* CEU */
140 /* Main LCD - RGB Mode */
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| H A D | sh7723.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * MD0: CPG - Clock Mode 0->3
8 * MD1: CPG - Clock Mode 0->3
9 * MD2: CPG - Reserved (L: Normal operation)
10 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
11 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
16 * GPIO_FN_xx - GPIO used to select pin function
17 * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
137 /* CEU */
156 /* Main LCD - RGB Mode */
[all …]
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| /openbmc/linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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| H A D | opengrok0.0.log | 1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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| H A D | opengrok1.0.log | 1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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| H A D | opengrok2.0.log | 1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)
4 2024-1
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