cpu/sh4a/clock-sh7722.c

1 // SPDX-License-Identifier: GPL-2.0
3  * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
5  * SH7722 clock framework support
14 #include <asm/clock.h>
29 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
35  * Default rate for the root input clock, reset this with clk_set_rate()
52 	return clk->parent->rate * mult;  in dll_recalc()
75 	return (clk->parent->rate * mult) / div;  in pll_recalc()
194 	CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[HWBLK_TMU]),
196 	CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &mstp_clks[HWBLK_CMT]),
197 	CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
200 	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
201 	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
202 	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
204 	CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
210 	CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]),
211 	CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
214 	CLKDEV_DEV_ID("renesas-ceu.0", &mstp_clks[HWBLK_CEU]),