cpu/sh4a/clock-sh7724.c

1 // SPDX-License-Identifier: GPL-2.0
3  * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
5  * SH7724 clock framework support
15 #include <asm/clock.h>
33 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
39  * Default rate for the root input clock, reset this with clk_set_rate()
58 	return (clk->parent->rate * mult) / div;  in fll_recalc()
78 	return clk->parent->rate * mult;  in pll_recalc()
90 /* A fixed divide-by-3 block use by the div6 clocks */
93 	return clk->parent->rate / 3;  in div3_recalc()
105 /* External input clock (pin name: FSIMCKA/FSIMCKB/DV_CLKI ) */
163 /* Indices are important - they are the actual src selecting values */
290 	CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
295 	CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[HWBLK_TMU0]),
296 	CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[HWBLK_TMU1]),
298 	CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &mstp_clks[HWBLK_CMT]),
299 	CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
300 	CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),
302 	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
303 	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
304 	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
305 	CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
306 	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
307 	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
313 	CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]),
314 	CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]),
316 	CLKDEV_DEV_ID("sh7724-ether.0", &mstp_clks[HWBLK_ETHER]),
329 	CLKDEV_DEV_ID("renesas-ceu.1", &mstp_clks[HWBLK_CEU1]),
334 	CLKDEV_DEV_ID("sh-vou", &mstp_clks[HWBLK_VOU]),
336 	CLKDEV_DEV_ID("renesas-ceu.0", &mstp_clks[HWBLK_CEU0]),