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/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/
H A Darmada-380-mpcore-soc-ctrl.txt1 Marvell Armada 38x CA9 MPcore SoC Controller
6 - compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
9 datasheet for the CA9 MPcore SoC Control registers
11 mpcore-soc-ctrl@20d20 {
12 compatible = "marvell,armada-380-mpcore-soc-ctrl";
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,scu.yaml13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
H A Darm,realview.yaml15 the earlier CPUs such as TrustZone and multicore (MPCore).
32 - description: ARM RealView Platform Baseboard for ARM 11 MPCore
34 multiprocessing with ARM11 using MPCore using symmetric
H A Darm,vexpress-juno.yaml46 in MPCore configuration in a test chip on the core tile. See ARM
58 cores in a MPCore configuration in a test chip on the core tile. See
71 CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
/openbmc/qemu/hw/cpu/
H A Darm11mpcore.c120 "mpcore-priv-container", 0x2000); in mpcore_priv_initfn()
126 /* Request the legacy 11MPCore GIC behaviour: */ in mpcore_priv_initfn()
136 /* The ARM11 MPCORE TRM says the on-chip controller may have
139 * the ARM11 MPCore test chip in the Realview Versatile Express
/openbmc/qemu/docs/system/arm/
H A Drealview.rst1 Arm Realview boards (``realview-eb``, ``realview-eb-mpcore``, ``realview-pb-a8``, ``realview-pbx-a9…
15 - ARM926E, ARM1136, ARM11MPCore, Cortex-A8 or Cortex-A9 MPCore CPU
H A Dxlnx-zynq.rst4 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based
11 - A9 MPCORE
/openbmc/linux/arch/arm/boot/dts/arm/
H A Darm-realview-eb-a9mp.dts27 model = "ARM RealView EB Cortex A9 MPCore";
30 * This is the Cortex A9 MPCore tile used with the
H A Darm-realview-eb-11mp.dts31 * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
35 * qemu-system-arm -M realview-eb-mpcore -smp cpus=4
H A Darm-realview-eb-mp.dtsi28 * This is the common include file for all MPCore variants of the
30 * and Cortex-A9 MPCore.
H A Darm-realview-eb-a9mp-bbrevd.dts27 model = "ARM RealView EB Baseboard Rev D Cortex A9 MPCore";
/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dtegra20-dc.txt44 interrupts = <0 65 0x04 /* mpcore syncpt */
45 0 67 0x04>; /* mpcore general */
/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-host1x.yaml241 interrupts = <0 65 0x04>, /* mpcore syncpt */
242 <0 67 0x04>; /* mpcore general */
377 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
378 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Dtimer.c9 #include "arm-mpcore.h"
H A Dpsci.c21 #include "arm-mpcore.h"
/openbmc/qemu/include/hw/timer/
H A Darm_mptimer.h2 * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dap.h23 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcpu.h34 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
/openbmc/linux/arch/arm/boot/dts/xen/
H A Dxenvm-4.2.dts6 * Cortex-A15 MPCore (V2P-CA15)
/openbmc/linux/Documentation/arch/arm/keystone/
H A Doverview.rst7 Keystone range of SoCs are based on ARM Cortex-A15 MPCore Processors
/openbmc/u-boot/arch/arm/include/asm/
H A Dmacro.h87 cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
98 cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */
/openbmc/qemu/hw/misc/
H A Darm11scu.c74 &mpcore_scu_ops, s, "mpcore-scu", 0x100); in arm11_scu_init()
/openbmc/qemu/hw/timer/
H A Darm_mptimer.c2 * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
61 /* Return conversion factor from mpcore timer ticks to qemu timer ticks. */
/openbmc/qemu/include/hw/intc/
H A Darm_gic.h25 * + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore GIC
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml27 The RPU MPCore can operate in split mode (Dual-processor performance), Safety

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