1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 209f455dcSMasahiro Yamada /* 37aaa5a60STom Warren * (C) Copyright 2010-2015 409f455dcSMasahiro Yamada * NVIDIA Corporation <www.nvidia.com> 509f455dcSMasahiro Yamada */ 609f455dcSMasahiro Yamada #include <asm/types.h> 709f455dcSMasahiro Yamada 809f455dcSMasahiro Yamada /* Stabilization delays, in usec */ 909f455dcSMasahiro Yamada #define PLL_STABILIZATION_DELAY (300) 1009f455dcSMasahiro Yamada #define IO_STABILIZATION_DELAY (1000) 1109f455dcSMasahiro Yamada 1209f455dcSMasahiro Yamada #if defined(CONFIG_TEGRA20) 1309f455dcSMasahiro Yamada #define NVBL_PLLP_KHZ 216000 1409f455dcSMasahiro Yamada #define CSITE_KHZ 144000 1509f455dcSMasahiro Yamada #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \ 167aaa5a60STom Warren defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) 1709f455dcSMasahiro Yamada #define NVBL_PLLP_KHZ 408000 18027638d3SBryan Wu #define CSITE_KHZ 136000 1909f455dcSMasahiro Yamada #else 2009f455dcSMasahiro Yamada #error "Unknown Tegra chip!" 2109f455dcSMasahiro Yamada #endif 2209f455dcSMasahiro Yamada 2309f455dcSMasahiro Yamada #define PLLX_ENABLED (1 << 30) 2409f455dcSMasahiro Yamada #define CCLK_BURST_POLICY 0x20008888 2509f455dcSMasahiro Yamada #define SUPER_CCLK_DIVIDER 0x80000000 2609f455dcSMasahiro Yamada 2709f455dcSMasahiro Yamada /* Calculate clock fractional divider value from ref and target frequencies */ 2809f455dcSMasahiro Yamada #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) 2909f455dcSMasahiro Yamada 3009f455dcSMasahiro Yamada /* Calculate clock frequency value from reference and clock divider value */ 3109f455dcSMasahiro Yamada #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) 3209f455dcSMasahiro Yamada 3309f455dcSMasahiro Yamada /* AVP/CPU ID */ 3409f455dcSMasahiro Yamada #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ 3509f455dcSMasahiro Yamada #define PG_UP_TAG_0 0x0 3609f455dcSMasahiro Yamada 377aaa5a60STom Warren #define CORESIGHT_UNLOCK 0xC5ACCE55 3809f455dcSMasahiro Yamada 3909f455dcSMasahiro Yamada #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) 4009f455dcSMasahiro Yamada #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) 4109f455dcSMasahiro Yamada #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) 4209f455dcSMasahiro Yamada #define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0) 4309f455dcSMasahiro Yamada #define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0) 4409f455dcSMasahiro Yamada 4509f455dcSMasahiro Yamada #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) 4609f455dcSMasahiro Yamada #define FLOW_MODE_STOP 2 4709f455dcSMasahiro Yamada #define HALT_COP_EVENT_JTAG (1 << 28) 4809f455dcSMasahiro Yamada #define HALT_COP_EVENT_IRQ_1 (1 << 11) 4909f455dcSMasahiro Yamada #define HALT_COP_EVENT_FIQ_1 (1 << 9) 5009f455dcSMasahiro Yamada 5109f455dcSMasahiro Yamada #define FLOW_MODE_NONE 0 5209f455dcSMasahiro Yamada 5309f455dcSMasahiro Yamada #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) 5409f455dcSMasahiro Yamada 557aaa5a60STom Warren /* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */ 567aaa5a60STom Warren #define SB_AA64_RESET_LOW 0x6000C230 577aaa5a60STom Warren #define SB_AA64_RESET_HIGH 0x6000C234 587aaa5a60STom Warren 5909f455dcSMasahiro Yamada struct clk_pll_table { 6009f455dcSMasahiro Yamada u16 n; 6109f455dcSMasahiro Yamada u16 m; 6209f455dcSMasahiro Yamada u8 p; 6309f455dcSMasahiro Yamada u8 cpcon; 6409f455dcSMasahiro Yamada }; 6509f455dcSMasahiro Yamada 6609f455dcSMasahiro Yamada void clock_enable_coresight(int enable); 6709f455dcSMasahiro Yamada void enable_cpu_clock(int enable); 6809f455dcSMasahiro Yamada void halt_avp(void) __attribute__ ((noreturn)); 6909f455dcSMasahiro Yamada void init_pllx(void); 7009f455dcSMasahiro Yamada void powerup_cpu(void); 7109f455dcSMasahiro Yamada void reset_A9_cpu(int reset); 7209f455dcSMasahiro Yamada void start_cpu(u32 reset_vector); 7309f455dcSMasahiro Yamada int tegra_get_chip(void); 7409f455dcSMasahiro Yamada int tegra_get_sku_info(void); 7509f455dcSMasahiro Yamada int tegra_get_chip_sku(void); 7609f455dcSMasahiro Yamada void adjust_pllp_out_freqs(void); 7709f455dcSMasahiro Yamada void pmic_enable_cpu_vdd(void); 78