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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
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H A Dst,stih407-irq-syscfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 On STi based systems; External, CTI (Core Sight), PMU (Performance
19 const: st,stih407-irq-syscfg
22 description: Phandle to Cortex-A9 IRQ system config registers
25 st,irq-device:
27 $ref: /schemas/types.yaml#/definitions/uint32-array
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/openbmc/linux/arch/arm/mach-omap1/
H A Dams-delta-fiq-handler.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
5 * Based on linux/arch/arm/lib/floppydma.S
14 #include <linux/platform_data/ams-delta-fiq.h>
15 #include <linux/platform_data/gpio-omap.h>
16 #include <linux/soc/ti/omap1-io.h>
22 #include "ams-delta-fiq.h"
23 #include "board-ams-delta.h"
27 * OMAP1510 GPIO related symbol copied from arch/arm/mach-omap1/gpio15xx.c.
79 * r8 - temporary
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
25 bool "OMAP15xx Based System"
31 bool "OMAP16xx Based System"
74 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
87 timer provides more intra-tick resolution than the 32KHz timer,
91 bool "Enable wake-up events for serial ports"
154 select FIQ
H A Dboard-ams-delta.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/board-ams-delta.c
5 * Modified from board-generic.c
19 #include <linux/mtd/nand-gpio.h>
29 #include <linux/platform_data/gpio-omap.h>
30 #include <linux/soc/ti/omap1-mux.h>
33 #include <asm/mach-types.h>
37 #include <linux/platform_data/keypad-omap.h>
41 #include "ams-delta-fiq.h"
42 #include "board-ams-delta.h"
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/openbmc/linux/drivers/irqchip/
H A Dirq-apple-aic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on irq-lpc32xx:
6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7 * Based on irq-bcm2836:
14 * - 896 level-triggered hardware IRQs
15 * - Single mask bit per IRQ
16 * - Per-IRQ affinity setting
17 * - Automatic masking on event delivery (auto-ack)
18 * - Software triggering (ORed with hw line)
19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are
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H A Dirq-ixp4xx.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on arch/arm/mach-ixp4xx/common.c
8 * Copyright 2003-2004 (C) MontaVista, Software, Inc.
28 #define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
30 #define IXP4XX_ICFP 0x10 /* FIQ Status */
33 #define IXP4XX_ICFH 0x1C /* FIQ Highest Pri Int */
35 /* IXP43x and IXP46x-only */
38 #define IXP4XX_ICLR2 0x28 /* Interrupt IRQ/FIQ Select 2 */
40 #define IXP4XX_ICFP2 0x30 /* FIQ Status */
44 * struct ixp4xx_irq - state container for the Faraday IRQ controller
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H A Dirq-sa11x0.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Dmitry Eremin-Solenikov
4 * Copyright (C) 1999-2001 Nicolas Pitre
15 #include <linux/irqchip/irq-sa11x0.h>
25 #define ICFP 0x10 /* IC FIQ Pending reg. */
39 reg &= ~BIT(d->hwirq); in sa1100_mask_irq()
48 reg |= BIT(d->hwirq); in sa1100_unmask_irq()
54 return sa11x0_sc_set_wake(d->hwirq, on); in sa1100_set_wake()
92 st->saved = 1; in sa1100irq_suspend()
93 st->icmr = readl_relaxed(iobase + ICMR); in sa1100irq_suspend()
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/openbmc/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Chen-Yu Tsai <wens@csie.org>
6 * Based on assembly code by Marc Zyngier <marc.zyngier@arm.com>,
7 * which was based on code by Carl van Schaik <carl@ok-labs.com>.
32 * The power clamps are located in the unused space after the per-core
133 writel((u32)entry, &cpucfg->priv0); in sunxi_set_entry_address()
144 sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff, in sunxi_cpu_set_power()
163 sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff, in sunxi_cpu_set_power()
176 if (readl(&cpucfg->cpu[cpu].status) & BIT(2)) in sunxi_cpu_power_off()
182 writel(0, &cpucfg->cpu[cpu].rst); in sunxi_cpu_power_off()
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/openbmc/linux/arch/arm64/kernel/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/irq.c
6 * Modifications for ARM processor Copyright (C) 1995-2000 Russell King.
7 * Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation.
66 /* irq stack only needs to be 16 byte aligned - not IRQ_STACK_SIZE aligned. */
97 panic("FIQ taken without a root FIQ handler\n"); in default_handle_fiq()
106 return -EBUSY; in set_handle_irq()
116 return -EBUSY; in set_handle_fiq()
119 pr_info("Root FIQ handler: %ps\n", handle_fiq); in set_handle_fiq()
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,ssi.txt4 be programmed in AC97, I2S, left-justified, or right-justified modes.
7 - compatible: Compatible list, should contain one of the following
9 fsl,mpc8610-ssi
10 fsl,imx51-ssi
11 fsl,imx35-ssi
12 fsl,imx21-ssi
13 - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
14 - reg: Offset and length of the register set for the device.
15 - interrupts: <a b> where a is the interrupt number and b is a
18 encoded based on the information in section 2)
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/openbmc/qemu/hw/intc/
H A Dbcm2836_control.c6 * Based on bcm2835_ic.c (Raspberry Pi emulation) (c) 2012 Gregory Estrade
17 * See the COPYING file in the top-level directory.
67 /* deliver a FIQ */ in deliver_local()
68 s->fiqsrc[core] |= (uint32_t)1 << irq; in deliver_local()
71 s->irqsrc[core] |= (uint32_t)1 << irq; in deliver_local()
84 s->irqsrc[i] = s->fiqsrc[i] = 0; in bcm2836_control_update()
88 if (s->gpu_irq) { in bcm2836_control_update()
89 assert(s->route_gpu_irq < BCM2836_NCORES); in bcm2836_control_update()
90 s->irqsrc[s->route_gpu_irq] |= (uint32_t)1 << IRQ_GPU; in bcm2836_control_update()
93 if (s->gpu_fiq) { in bcm2836_control_update()
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H A Dbcm2835_ic.c4 * Heavily based on pl190.c, copyright terms below:
12 * See the COPYING file in the top-level directory.
29 #define FIQ_CONTROL 0x0C /* FIQ register */
42 if (s->fiq_enable) { in bcm2835_ic_update()
43 if (s->fiq_select >= GPU_IRQS) { in bcm2835_ic_update()
45 set = extract32(s->arm_irq_level, s->fiq_select - GPU_IRQS, 1); in bcm2835_ic_update()
47 set = extract64(s->gpu_irq_level, s->fiq_select, 1); in bcm2835_ic_update()
50 qemu_set_irq(s->fiq, set); in bcm2835_ic_update()
52 set = (s->gpu_irq_level & s->gpu_irq_enable) in bcm2835_ic_update()
53 || (s->arm_irq_level & s->arm_irq_enable); in bcm2835_ic_update()
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H A Daspeed_vic.c9 * the COPYING file in the top-level directory.
27 * read-modify-write sequence).
47 uint64_t new = (s->raw & s->enable); in aspeed_vic_update()
50 flags = new & s->select; in aspeed_vic_update()
52 qemu_set_irq(s->fiq, !!flags); in aspeed_vic_update()
54 flags = new & ~s->select; in aspeed_vic_update()
56 qemu_set_irq(s->irq, !!flags); in aspeed_vic_update()
74 if (s->sense & irq_mask) { in aspeed_vic_set_irq()
75 /* level-triggered */ in aspeed_vic_set_irq()
76 if (s->event & irq_mask) { in aspeed_vic_set_irq()
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/openbmc/qemu/tests/tcg/aarch64/system/
H A Dboot.S6 * Loosely based on the newlib/libgloss setup stubs. Using semihosting
13 * w0 - semihosting call number
14 * x1 - semihosting parameter
32 ventry curr_sp0_fiq /* Fiq/vFIQ */
38 ventry curr_spx_fiq /* FIQ/vFIQ */
44 ventry lower_a64_fiq /* FIQ/vFIQ */
50 ventry lower_a32_fiq /* FIQ/vFIQ */
100 * Setup a flat address mapping page-tables. Stage one simply
108 bic x1, x1, #(1 << 30) - 1 /* 1GB alignment*/
109 add x2, x0, x1, lsr #(30 - 3) /* offset in l1 page table */
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/openbmc/linux/sound/soc/fsl/
H A Dimx-pcm-fiq.c1 // SPDX-License-Identifier: GPL-2.0+
2 // imx-pcm-fiq.c -- ALSA Soc Audio Layer
6 // This code is based on code copyrighted by Freescale,
12 #include <linux/dma-mapping.h>
26 #include <asm/fiq.h>
28 #include <linux/platform_data/asoc-imx-ssi.h>
30 #include "imx-ssi.h"
31 #include "imx-pcm.h"
48 struct snd_pcm_substream *substream = iprtd->substream; in snd_hrtimer_callback()
51 if (!atomic_read(&iprtd->playing) && !atomic_read(&iprtd->capturing)) in snd_hrtimer_callback()
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H A Dimx-pcm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * This code is based on code copyrighted by Freescale,
12 #include <linux/dma/imx-dma.h>
15 * Do not change this as the FIQ handler depends on this size
35 return -ENODEV; in imx_pcm_dma_init()
47 return -ENODEV; in imx_pcm_fiq_init()
H A Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
17 // manually skip this data in the FIQ handler. With sampling rates different
19 // between pcm data and GPIO status data changes. Our FIQ handler is not
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
66 * (bit-endianness must match byte-endianness). Processors typically write
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/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Drelocate.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * relocate - i.MX27-specific vector relocation
8 #include <asm-offsets.h>
18 * However, these ROM-based vectors actually just perform indirect
19 * calls through pointers located in RAM at SoC-specific addresses,
30 * 0x0000001c FIQ indirect branch to [0xffffff04]
32 * In order to initialize exceptions on i.MX27, we must copy U-Boot's
41 ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
45 ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */
46 stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */
/openbmc/linux/fs/fuse/
H A Dfuse_i.h3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
23 #include <linux/backing-dev.h>
41 /** Bias for fi->writectr, meaning new writepages must not be sent */
100 /** The sticky bit in inode->i_mode may have been removed, so
116 /* Files usable in writepage. Protected by fi->lock */
241 /** RB node to be linked on fuse_conn->polled_files */
359 * - FR_ABORTED
360 * - FR_LOCKED (may also be modified under fc->lock, tested under both)
393 /** virtio-fs's physically contiguous buffer for in and out args */
406 * Input queue signalling is device-specific. For example, the /dev/fuse file
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H A Dinode.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
78 sl->forget = fuse_alloc_forget(); in fuse_alloc_submount_lookup()
79 if (!sl->forget) in fuse_alloc_submount_lookup()
97 fi->i_time = 0; in fuse_alloc_inode()
98 fi->inval_mask = ~0; in fuse_alloc_inode()
99 fi->nodeid = 0; in fuse_alloc_inode()
100 fi->nlookup = 0; in fuse_alloc_inode()
101 fi->attr_version = 0; in fuse_alloc_inode()
102 fi->orig_ino = 0; in fuse_alloc_inode()
103 fi->state = 0; in fuse_alloc_inode()
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/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9rl.h2 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h]
7 * Based on AT91SAM9RL datasheet revision A. (Preliminary)
20 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
/openbmc/linux/Documentation/arch/arm64/
H A Dbooting.rst9 This document is based on the ARM booting document by Russell King and
13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
91 - As of v3.17, all fields are little endian unless stated otherwise.
93 - code0/code1 are responsible for branching to stext.
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/openbmc/linux/arch/arm/include/asm/
H A Dptrace.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2003 Russell King
27 (((regs)->ARM_cpsr & 0xf) == 0)
31 (((regs)->ARM_cpsr & PSR_T_BIT))
38 ((((regs)->ARM_cpsr & PSR_J_BIT) >> (__ffs(PSR_J_BIT) - 1)) | \
39 (((regs)->ARM_cpsr & PSR_T_BIT) >> (__ffs(PSR_T_BIT))))
45 ((regs)->ARM_cpsr & MODE_MASK)
48 (!((regs)->ARM_cpsr & PSR_I_BIT))
51 (!((regs)->ARM_cpsr & PSR_F_BIT))
59 unsigned long mode = regs->ARM_cpsr & MODE_MASK; in valid_user_regs()
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/openbmc/linux/arch/arm64/kvm/hyp/
H A Dexception.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012,2013 - ARM Ltd
8 * Based on arch/arm/kvm/emulate.c
9 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
63 vcpu->arch.ctxt.spsr_abt = val; in __vcpu_write_spsr_abt()
71 vcpu->arch.ctxt.spsr_und = val; in __vcpu_write_spsr_und()
77 * The EL passed to this function *must* be a non-secure, privileged mode with
85 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
86 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
134 if (kvm_has_mte(kern_hyp_va(vcpu->kvm))) in enter_exception64()
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